Low power VLSI circuit modeling techniques

Low power VLSI circuit modeling techniques

In this decade there is huge demand for low power VLSI semiconductor chips. In order to achive low power, power consumption should be minimized at CMOS MOSFET level. In this article, various techniques which are available for minimizing the power consumption at different abstraction levels are discussed in detail. With the help of this article, VLSI design engineers can pick the right methodology with suitable process techniques to reach their required goal.

Introduction

VLSI Integrated circuits are evolved about four decades ago. VLSI chip designers are still looking for enhancement in the performance of an integrated circuit by accomplishing the less area, low power utilization. Scaling techniques has been evolved to achieve these criteria. While scaling the power and area, various challenges encounters those are leakage currents (sub threshold leakage, gate tunneling, hot electron effect, impact ionization, gate induced drain leakage current etc).

Keeping in mind all those performance affecting parameters, VLSI designers produced various design mythologies. There are various techniques to achieve low power design. All this techniques are discussed in detail in this article.


Sources of power consumption in CMOS devices

The total power consumption of CMOS VLSI device can be expressed us...