FDSOI technology gets a massive push from two big innovators/investors of this technology. STMicroelectronics, a company which has put significant intellectual effort in making this technology a beneficial in terms of performance cost and other factors, is now strengthening its partnership with Globalfoundries in creating a new jointly operated 300 mm chip manufacturing facility at its own presently operating semiconductor manufacturing facilities at Crolles, France. This new factory to produce 620,000 300mm wafer per year when it achieves full capacity by 2026.
The new fab to serve the customers from Europe and worldwide. FDSOI technologies to be used at this fab include FDX technology, and the nodes down to 18 nm covering applications such as automotive IOT and mobile. With Europe setting a goal of reaching 20% of worldwide semiconductor production by 2030, this new manufacturing facility supported by state of France is a major contributor in reaching that goal.
In comparison to other technologies, FDSOI offers both performance and cost advantage, still in line with Moore's Law. To some of the readers who are less aware of the benefits of FDSOI or other technologies, here reproduced below is the earlier interview article published in EE Herald.
While the semiconductor fab industry facing big hurdle in scaling further down after 28nm without increase in cost, blessing for the industry comes in the form of new technology called fully depleted silicon-on-insulator (FDSOI). FDSOI can take Moores law down to 10nm. STMicroelectronics is already making 28nm chips out of its Crolles, France fab using FDSOI, ST and its partners have also licensed FDSOI tech to leading foundry Samsung to produce 28nm chips using FDSOI. Below is the Q & A interaction with ST's Rajamohan Varambally, Director, Central CAD and design solutions, STMicroelectronics India.
Q. What is FD-SOI?
FD-SOI stands for Fully Depleted Silicon On Insulator. Planar fully depleted silicon-on-insulator (“planar FD”, or equivalently “FD-SOI”) transistors are planar CMOS transistorsfabricated in a very thin layer of silicon sitting over a layer of buried oxide (BOX). They are therefore ‘ultra-thin body’ (UTB) devices: the electrical conduction channel that forms between source and drain is confined to this ultra-thin silicon layer under the gate oxide.
Q. What makes this process better than other deep-node semiconductor chip fabrication tech?
1. Immunity to Short-Channel Effects
Ultra-thin body and BOX ensures all electrical paths between source and drain are very close to the gate, and the lattertherefore maintains excellent electrostatic control over the channel. As a result, sub-threshold slope, DIBL and other short-channel effects exhibit excellent values
2. Reduced Variability
· The absence of doping or pocket implants in the channel helps to control the electrostatic characteristics and tune the threshold voltages. No doping or implants eliminates the major issue of random dopant fluctuation.
3. Low source/drain capacitance, lower leakage and latch-up immunity due to BOX
Q. If fabless companies decide to use FD-SOI process, what are the issues they should address while moving their design to FD-SOI, particularly when they are using 3rd party IPs blocks which are not FD-SOI ready?
The design method and tools used in 28nm bulk is applicable to FD-SOI as well. Using the foundation IPs and Physical DK provided by ST, any fabless company can make their design in FD-SOI
IP blocks have to be FD-SOI compatible; if not, those blocks need to be migrated. ST has proven that the porting effort is not difficult or challenging.
Q. What is the benefits to end customer both in terms of performance and cost?
1. With 28nm FD-SOI we can offer customers equivalent performance to 20nmbulk CMOS for a much lower cost, providing better power efficiency than 28HPM or 28HPC.. The performance-power ratio is quite simply the best in the market today.
2. Designing in 28nm FD-SOI is like designing in bulk. There is no need to invest in new tools or to learn new design methods.28nm FD-SOI is lower in cost than 28HPM and 28HPC as the number of masks required is reduced by more than 25%
Q. Is it possible to still build 3-D structures (such as finFETs) using FD-SOI?
At least until the 10nm node, there is no need real need to add the complexity of 3D structures to an inherently more simple process, so, while we continue to develop expertise in 3D structures, our plan is to stay with 2-D transistors as it meets the performance expectation.
Q. Can FD-SOI be used for chips other than logic such as analog and RF?
FD-SOI analog performance is far better than Bulk. It is faster, provides better gain and better parasitic-capacitance noise immunity. This translates into easier design and better performance for RF, mixed signal and high speed interfaces like serializers/deserializers.
Q. When industry can expect volume production of chips using FDSOI?
1. FD-SOI is already qualified for volume production at our ST, Crolles facility
2. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production
Q. Finally can FD-SOI help semiconductor industry still extend Moore's Law into deeper nodes such as 7 nm?
1. In the past, the cost per gate decreased each time the industry moved to a new technology node. From 20 nm onwards the cost per gate increases. So by choosing 28nm FD-SOI, the customer delays this effect. In the meantime the industry will see an improvement in cost, performance and power efficiency compared to the previous node (See the below picture).
2. UTBB FD-SOI is scalable down to 10nm Technology Node. Electrostatic control achieved by thinning Tbox (See the below picture).
Pic above: Rajamohan Varambally, Director, Central CAD and design solutions, ST Microelectronics India