There is lot to learn from food cooking for today's VLSI design engineers who are designing SoCs at deep nodes such as 7 nm. A simple yet tasty food can be cooked from very few ingredients. The same chef can use lot more ingredients to cook a richly tasting food.
Similarly SoC design is turning out to be how you mix and match various IPs, foundries and software and hardware tools in developing your SoC where you also end up designing the end product. The secret sauce will always be there to make your SoC unique. A careful chef personally visits market to select the best vegetable or any such ingredients. So is the VLSI designer in selecting the IPs, tools and process. The recently concluded VLSI specific event DVCON India 2017 held in Bangalore is one such place where VLSI chip-chefs can pick some ideas.
In case of selection of tools you have these three vendors Synopsys, Cadence and Mentor Graphics who hardly leave anything not offered. But the new players keep emerging, most of the time to get acquired by these three. It is a continuous trend. They are also leading IP vendors.
DVCON was also full of presentation from these vendors or semiconductor customers who have leveraged their tools to produce some unique recipe.
Interesting talk at the event was on ESL, where VLSI designers arguing on how important and beneficial it is.
Key points from DVCON 2017:
Picture: Christopher Tice of Synopsys explaining SoC verification challenges
