HomeNewsNews Details
News Details
Date: 11-06-17

Atomic layer deposition and EUV takes chip scaling to 5nm replacing finFET with NW/NS

To take VLSI chip integration further FinFET is replaced by Nanowires with metal gate all around. The CEA Leti, imec and IBM, all are making this technology realistic. IBM is little ahead by announcing a breakthrough process to use Nano sheets to make nano wires by using extreme ultraviolet (EUV) lithography and other innovation in nano-tech.

Alternate thin silicon and metal sheets are used to form laterally fabricated Silicon nano wires which are wrapped/surrounded by metal. IBM has not disclosed about the methods used to deposit atomic scale films of metal and semiconductor layers. The advanced atomic-layer epitaxial deposition processes may have been used to achieve required accuracy and also to deposit semiconductor materials like Germanium over Silicon to make the Si-Ge channel. The role of semiconductor equipment companies such as LAM Research, Applied Materials, and ASM is key in making 5nm chips.

The interesting part of the process is exploring EUV litho to etch silicon sheets into  nano-wire like formation for any customised sizes whether to achieve low power consumption or higher speed. All this is done without using multiple patterning to save from using higher number of expensive photomasks. Interestingly lot of traditional semiconductor equipments may have been employed although the process is different from FinFET.

So the secret sauce to bake these 5 nm chips is: Depositing of Silicon nano sheets and metal layers, including the dielectric layer and effectively using EUV litho to etch the shapes.                                                             

IBM and its semiconductor research partners GLOBALFOUNDRIES and Samsung to present 5 nm breakthrough at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan.

By using this process it is possible to have 30 billion switches on a finger-nail sized IC chip. With 30 billion transistors in a thumbnail size chip, VLSI processor/CPU architects are free to have lot more hardware accelerators to handle streaming high-definition video/audio. So you'll see a lot more  on-chip vector computing, and all this at less power consumption than the present one. Cognitive computing, AI, and Machine Learning will grow faster with such chips available for engineers.       

IBM said "Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices."

Globalfoundries planning to commercialize 7nm in 2018 by using IBM's SiGe and EUV litho before commercializing 5nm tech.

IBM said by using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. This adjustability permits the fine-tuning of performance and power for specific circuits.

IBM ranks this silicon nano sheet based 5 nm chip fabrication equivalent to its  other inventions such as single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

To tell you about other innovator in this area, in 2016 Belgium based semiconductor research company imec had  reported for the first time the CMOS integration of vertically stacked gate all around (GAA) silicon nanowire MOSFETs.

France based nano-tech researcher CEA-Leti had presented "Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs,  a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFETs" at the 2016 IEEE International Electron Devices Meeting (IEDM) held in San Francisco.

Leti presented its research on the very first functional devices featuring stacked nano wire transistors with integrated inner spacers to reduce parasitic capacitances and SiGe source drain  stressors to boost performance.

Leti Said both are the building blocks for the 5nm node to further the scaling limits of CMOS technology as a natural progression from FinFETs.

Though imec and Leti have not publicly announced full availability of 5 nm process, they mostly having this NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) technology ready for its partners.

1 Comments
Default user
Default user
Fred Chen 12-06-17
The width can be varied continuously without EUV by adjusting the width between spacers..
Related News