To improve the contact resistance and device performance of Germanium based semiconductor devices, Japan university researcher used germanides of metals at the metal-germanium interface with suitable surface crystal plane. This research is featured in the November 2016 issue of the online JSAP Bulletin.
The next - generation electronics draws great curiosity and interests in semiconducting element germanium due to its high electron and hole mobilities. Germanium transistor devices with high-mobility such as metal-insulator field-effect transistors (MISFETs) have been demonstrated where parasitic resistance and the suppression of off-state leakage at the source and drain gates still inhibit the performance of these devices.
The band structure in a metal and semiconductor where variation in energy levels can cause an obstacle hindering the transport of electrons called Schottky barrier height.
Fermi level pinning is one of the main contributors to the contact resistance in germanium devices where band bending at the interface increases the SBH.
Dipole as a hypothesis is induced at the electron wave function meeting the metal surface. The electron density at this surface is decreased as and when the requirement of the effect is reduced.
The Fermi level pinning effects greatly alleviated due to the measurement of the current voltage characteristics at metal - germanides interfaces as founded by Tomonori Nishimura, Takeaki Yajima, and Akira Toriumi upon the free electron density of metal germanides of 1-2 orders of magnitude less than metals.
When the (111) crystalline plane was used, the SBH was diminished to a greater extent as noted by the researchers. The germanium-germanide interfaces remained high because of the contact was made along the (110) plane the barrier to electron transport.
The report concluded according to their findings indicated that the SBH at the direct metal-Ge interface is practically controllable, and the contact resistance in Ge n-MISFETs can be considerably reduced.