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Date: 31-05-16

Sheet like insulation layer for semiconductor package substrates

To make the semiconductor chips used in smart phones further thinner, Panasonic has developed a sheet-form encapsulation material for coreless package substrates. The sheet-form encapsulation material which is scheduled for mass production from June 2016 is also reduces the cost making it suitable for large-area encapsulation.

semiconductor packaging sheet

The new coreless process requires an insulation material for coreless processes that shows good productivity and eliminates the need for thin core materials as well as laser drilling processing. Panasonic used its resin design technology to develop a sheet-form encapsulation material for coreless package substrates.

Panasonic shares below features of this semiconductor packaging material:
A sheet-form encapsulation material with a uniformly produced insulation layer thickness is ideal for the new coreless process1, as it eliminates the need for laser drilling processing. The insulation layer for a package substrate can be produced using a large-area press process, enabling the mass production of packages at lower cost.
- Sheet thickness is available in the range of 20 - 200 µm.
The high rigidity of the thin sheet encapsulation material minimizes any warpage of packages and contributes to a thinner profile. Modulus of elasticity: 17000 MPa at 25°C.
A low shrinkage rate of material ensures connection reliability to be maintained during high-temperature reflow processes, increasing the production yield of the package assembly process.
- Shrinkage rate: 0.003%

Detailed description of its features as provided by Panasonic:
1. A sheet-form encapsulation material with a uniformly produced insulation layer thickness is ideal for the new coreless process, as it eliminates the need for laser drilling processing. The insulation layer for a package substrate can be produced using a large-area press process, enabling the mass production of packages at lower cost.

Conventional package substrates are produced from thin core material including glass cloth, and via [3] forming requires laser drilling processing and through-hole copper plating for connection between both surfaces, resulting in a high-cost process. In contrast, a coreless package substrate using the new copper pillar resin encapsulation process [4] can produce copper pillars by copper plating employing an additive process that eliminates the need for laser drilling processing, leading to a thinner package profile and lower cost. To enable the mass production of package substrates, an easily-managed material is needed that allows the press-forming of a uniform insulation layer over a large area. Panasonic has commercialized a product featuring sheet-formed encapsulation material of uniform thickness that is optimized for coreless processes by applying a unique filler design and proprietary resin design technology. Adoption of this material for the insulation layer enables press forming over a large area, contributing to the mass production of packages at lower cost. Sheet thicknesses from 20 µm to 200 µm can be produced for the wide variety of package types required by customers.
2. The high rigidity of the thin sheet encapsulation material minimizes any warpage of packages and contributes to a thinner profile.

A coreless package substrate carries the risk of increased warpage if its insulation layer is very thin, risking handling problems during the assembly process. To secure reliability in the assembly process, minimal warpage is required, especially for a thin material. The company's unique filler design and resin design technology have achieved high rigidity and strength even with extremely thin sheets, reducing package warpage while maintaining a thin profile.
3. A low shrinkage rate of material ensures connection reliability to be maintained during high-temperature reflow processes, increasing the production yield of the package assembly process.

Since the package assembly process may undergo multiple high temperature reflow processes, a smaller thermal shrinkage rate is required for package substrate materials to prevent bonding defects between the conductor on the substrate and the IC chip. This material has achieved a low shrinkage rate by developing a unique filler design technology that will achieve improved production yield in the assembly process.

New source: panasonic.com

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