In the extremely tough semiconductor chip fabrication technology, Samsung is number one in getting there at 14 nm and also it expects to make 10 nm chips in 2016, earlier compared to its competitor's roadmap. For some reason Intel is not as fast as earlier when it comes to node scaling. Another player TSMC is doing better than Intel.
With the 16 nm chip production from TSMC going in full speed. TSMC working even faster to make 10 nm chips for smartphone and such multicore SOC applications. ARM announced the first multicore, 64-bit ARM v8-A processor test chip based on TSMC's 10 nm FinFET process technology. It's not just at 10 nm even at 7 nm both are working with long-term agreement .
While Intel expands into non-PC and server markets, (forget smartphones market, even otherwise) it has to compete with ARM processor core powered SOC chips in many new emerging large volume applications including high MIPS demanding self driving ADAS automotive electronic systems. Some of the applications in the IOT domain too also demand higher processing power but at extremely low power. In that sense earlier production of 10 nm by Intel gives it a competitive edge over ARM. Intel has to target broader market for growth. Is Intel waiting for EUV to stay away from expensive multiple pattern masks for lithography?
Though Intel has not announced what exactly called test chip in the 10 nm node, it might have done that already. Intel is also a now foundry service provider where it may have to provide access to third-party EDA tools from leading vendors such as Synopsys, Cadence and Mentor Graphics. For TSMC, the above said EDA partners are essential and vice versa. All the three top EDA vendors have announced ready VLSI design software tools and support for TSMC 10 nm. Non-PC SOC development involves integration of huge number of third-party silicon IP demanding single-team like working across different organisations and vendors. So Intel has to build a developer eco for its new businesses, where ARM and TSMC partnership is ahead of Intel.
Well, why not 14 nm or 16 nm FDSOI before 10 nm finFET. 16 nm FDSOI offers both cost and performance advantage compared to 10 nm FinFET. Here globalfoundries and also Samsung which have invested into FDSOI, can add more value to the deep node semiconductor chip market. STMicroelectronics which is behind the development of FDSOI can offer FDSOI SOC chips for ADAS automotive electronic systems. For FDSOI also there is a challenge of building VLSI software( both tools and IP) developer eco.
In the emerging markets such as IOT, self driving/ADAS automotive and also smart homes, the first-to-market advantage is significant. So the race is even closer between the foundries and the merchant chipmakers.
Also another trend to note is: At nodes lower than 28 nm, Moore's Law gets slightly distorted and slowed, where the benefits is not as good as earlier node transition. Except for the packing of more number of transistors, there is no significant increase in the speed and low power consumption.
3-D chip fabrication and packaging, on chip photonics, on chip RF supporting 5G might look more commercially viable compared to scaling down to deeper nodes, unless some breakthrough happens in non-silicon compound semiconductor material based chips at deeper nodes.