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Date: 06-07-15

Less power consuming 65 nm semiconductor fab process by Toshiba

Toshiba is not limiting its semiconductor fabrication research focus to pure memory alone, it has announced a new flash memory embedded process based on 65nm logic process. The chips made from which consume lesser power than the present mainstream technology. Toshiba also developed single-poly non-volatile memory (NVM) process based on 130nm logic and analog power process. By using these processes, Toshiba to make devices such as microcontrollers, wireless communication ICs, motor controller drivers and power supply ICs. Toshiba highlights the importance of IoT market for products fabricated using these processes where low-power consumption is important in applications such as wearable and medical electronics.

Toshiba plans to release sample BLE (Bluetooth Low Energy) IC, short-range wireless ICs in fiscal year 2016. The company also plans to apply the 65nm process to its wireless communication IC product family that can optimize use of low power consumption characteristics, including NFC (Near Field Communication) controllers, and contactless cards.

Toshiba said it has adopted SST's third-generation SuperFlash cell technology, in combination with its own 65nm logic process technology. Toshiba has improved both circuits as well as manufacturing processes in developing its ultra-low power consumption flash embedded logic process. The new process help Microcontroller chips to consume power approximately 60% less compared to the present mainstream technology, claims Toshiba.

Another advantage of the new process according to Toshiba is "shorter development time, as application software can be easily written and rewritten to flash memory during development."

The NVM embedded process developed uses YMC’s (Yield Microelectronics Corporation) single-poly MTP (Multi-time programmable) cells on Toshiba’s 130nm logic process technology.

"Applying MTP specifications for write times improves the new process’s performance while limiting increased steps in mask pattern lithography to three or fewer, and even none." says Toshiba.

Toshiba also to use MTP to adjust output accuracy and expand its product line-up in fields where higher accuracy is essential, such as power management ICs.

The sample quantity of IC chips made using these processes is scheduled to be available in 4th quarter of 2015 (130nm-NVM) and the 2nd quarter of 2016 (65nm- flash).

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