Ramon Chips developing Radiation Hardened ASIC solutions for space applications, has licensed the CEVA-X1643 for its RC64 64-core parallel processor for compute intensive space electronics applications. Ramon will integrate sixty-four CEVA-X1643 DSPs into the RC64 processor provide higher computing on-board in satellites deployed for communications, earth observation, science and many other applications.
RC64 is a 65nm CMOS parallel processor, providing 384 GOPS, 38 GFLOPS and 60 Gbps data rate. Each of the 64 CEVA-X1643 cores has direct access to a 4MB shared memory, in addition to private memories and caches, including support for ECC. The cores are managed at runtime by a hardware synchronizer that automatically manages parallel tasks, enabling nearly-perfect dynamic load balancing among the cores and facilitates task switching at a very high rate and very low latency.
"The underlying processor technologies in satellites have remained mostly unchanged for nearly two decades, resulting in poor performance for today's processing-intensive applications," said Prof. Ran Ginosar, CEO at Ramon Chips. "Our new RC64 processor based on the CEVA-X1643 DSP promises to change this, bringing outstanding performance, programmability and scalability to next-generation satellite systems, and enabling the massively parallel processing required for many of the latest satellite communications, research and observation applications."
"We are excited to work with Ramon Chips on the development of their RC64 64 DSP satellite processor, one of the largest multi-core use cases for our DSPs," said Eran Briman, vice president of marketing at CEVA. "Massively parallel processing is key for high performance space computing and the CEVA-X1643 delivers exceptional capabilities for the demanding use cases that Ramon is targeting."
Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities are the notable features of CEVA-X1643 DSP core. The 32-bit programming model of CEVA-X1643 DSP core is suitable for high level of parallelism and process up to eight instructions per cycle, and 16 SIMD operations per cycle. Featuring high performance AXI-based memory sub-system, adopts fully-cached instruction and data memories with ECC, supports multi-core and many-core architectures, and includes an innovative Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. For more information, visit http://www.ceva-dsp.com/CEVA-X1643.