Rudolph Technologies said one of the major outsourced semiconductor chip assembly and test manufacturer has selected Rudolph's JetStep Advanced Packaging Lithography System for evaluation , which will be used to develop copper (Cu) pillar bumping and through silicon via (TSV) processes used in the development of next-generation flip chip technology.
“Copper pillar bumping and TSV have emerged as leading interconnect technologies for advanced packaging, and Rudolph is committed to partnering with customers to develop these next-generation processes. The JetStep system has demonstrated excellent performance on copper pillar and TSV applications in our applications lab, and we look forward to replicating this performance using production wafers at the customer site,” states Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “We expect to see significant productivity and process improvement over this customer’s existing lithography systems.”
“We are pleased to ship the JetStep system to a third customer,” adds Mike Plisinski, executive vice president and chief operating officer. “This agreement demonstrates not only an increasing emphasis in the back-end on productivity and cost-of-ownership, but also the growing adoption of the JetStep system for advanced packaging lithography.”