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Date: 16-01-15

Latest EDA update from Cadence: 3D audio DSP, memory, interface IP and AMS tool

Tensilica HiFi 4 audio/voice digital signal processor (DSP) intellectual property (IP) core from Cadence supports new and interesting object-based audio standards, where individual sounds become objects that can be placed anywhere in a room. The separate sounds sources are mixed on the fly at each location where they are played back. DSP calculates where the sound should emanate irrespective of location of speakers . Single core HiFi 4 DSP -based chip is capable to handle such processing.

HiFi 4 DSP supports four 32x32-bit multiplier-accumulators (MACs) per cycle with 72-bit accumulators, more than double the performance of other audio DSPs for computationally intensive functions such as fast Fourier transform (FFT) and finite impulse response (FIR) and also supports for eight 32x16-bit MACs per cycle under specified conditions, as per Cadence.
HiFi 4 DSP also offers 4 very long instruction word (VLIW) slot architecture capable of issuing two 64-bit loads per cycle.

Another music related interesting feature in Cadence Tensilica HiFi Audio/Voice digital signal processor (DSP) family is HARMAN’s Clari-Fi music restoration technology has been ported to these cores.

HARMAN’s Clari-Fi music restoration technology automatically analyzes and improves the audio quality of all types of compressed, digitized music sources, reconstructing the information lost during the compression process
Some of the other VLSI IP cores announced recently by Cadence includes:
Cadence has announced the availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).

Cadence announced Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes.

Cadence unveiled first multi-protocol DDR4 and LPDDR4 intellectual property (IP) Solution. The Cadence DDR controller and PHY IP can scale up to 3200Mbps to take advantage of higher performance DDR4 and LPDDR4 DRAMs when they become available, without having to redesign their systems on chip (SoCs).

On the VLSI design tool front, Cadence new Virtuoso Liberate analog IC characterization tool offers dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os. Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional “divide and conquer” FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff, says Cadence.

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