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Date: 16-01-15

10X boost in VLSI design throughput using latest place and route from Synopsys

Synopsys has recently released its 2014.12 version of new IC Compiler II place and route solution, which the company claims as game-changing successor to IC Compiler, the older place and route VLSI chip design tool from Synopsys. The new version offers features such as multi-objective concurrent clock and data optimization, advanced low power optimization techniques and early support for 10-nm process technology.

The immediately available IC Compiler II is a full-featured, production-ready netlist-to-GDSII implementation system supports ultra-high capacity design planning, unique new clock-building technology and advanced global analytical closure techniques, enabling it to deliver a 5X speed-up in implementation runtime with half the memory and half the iterations required to achieve target performance. Synopsys claims all this results in 10X boost in design throughput.

The highlighted features of IC Compiler II also include electro-migration (EM) analysis, transparent interface optimization (TIO).

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