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Date: 16-12-14

CEA Leti presented 3D building of transistors at IEDM

Semiconductor research organisation CEA-Leti presented a paper on how to Stack transistor sequentially in the same process flow for 3D-VLSI, at ongoing semiconductor manufacturing technology IEDM 2014. This technology is called as CoolCube.

“The technology is designed to allow a connection of the stacked active layers on a nanometric scale, with a very high density, due to their alignment by a standard lithographic process,” said Maud Vinet, Leti’s advanced CMOS laboratory manager, who will give the presentation. “This 3D concept should allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation.”

CoolCube consumes less thermal energy in manufacturing transistors by using low temperature fabrication process to vertical integrate transistors without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

Leti is presenting a total of 17 papers including four invited papers, at IEDM 2014.

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