The researchers at Stanford University in US have developed a 3-D cube rather a chip integrating complex logic functions and nonvolatile high density memory with integration levels comparable to today's most advanced silicon VLSI semiconductor chip fabrication. The new device also cost less to produce and it consume far lesser power than silicon CMOS chip. It is a culmination of achievements, what researchers at Stanford University have done in the past 1 to 2 years in non-silicon logic and memory device research area.
The three basic achievements include development of high-density nonvolatile memory RRAM using a better and simpler process than the present flash memory manufacturing. The second achievement is designing a logic chip using carbon nano tubes. Stanford researchers have developed logic chips using carbon nano tubes in 2013, but they were not that dense compared to today's silicon chips, recently they seem to have achieved higher level of integration comparable to today's silicon chips. The third important achievement is stacking of logic and memory devices one above the other in a far more simpler process compared to today's silicon semiconductor chip stacking using through silicon via (TSV).
They have combined all these three achievements to build a three-dimensional integrated-circuit multi-storey device with computing and storage potential comparable to a supercomputer on a chip. If all what claimed by Stanford researcher's is true, someday a cube/3d-chip made based on this technology can turn a smart phone in to a supercomputer.
Some of the key achievements by the researchers in building multi-storey logic and memory combined cube includes:
To create RRAMs, Linda He Yi, a researcher at Stanford used a not so high temperature process called "diblock copolymer self-assembly lithography", which can be well employed for volume production too. Much of the fabrication was done using the material processing equipment available in their university. The idea of researchers was to build RRAM on silicon substrate, that means utilising the present semiconductor manufacturing equipment to maximum extent.
Well if this is about achieving high-density nonvolatile memory, in the month of September 2013, Stanford researchers have also announced the development of a computer using chips made out of carbon nano tubes. At that time, the carbon nano tube based processor chip has limited number of switching devices in offering high-performance logic functions. But now based on the latest announcement, they were able to build carbon nano tube based logic functions comparable to the density of today's silicon logic chips. The issues they were facing in designing nano tube based chips was, making hundred percent aligned carbon nano tubes, a small deviation of single carbon nano tube will make the whole device useless. It looks like they have overcome this challenge and were able to integrate more carbon nano tubes in smaller space. They have grown carbon nano tubes on a quartz wafers. These grown carbon nano tubes were transferred to the silicon wafer by using a metal film like a tape.
So how did they stack the logic and memory layers to form the multi-storey device? What helped these researchers was, the carbon nano tubes logic layer and RRAM memory layer was assembled using low temperature fabrication process, so that when they build the next layer, the bottom layer stays good unlike silicon.
The researchers behind this technology includes Subhasish Mitra, H.-S. Philip Wong, Williard R. and Inez Kerr Bell of Stanford’s School of Engineering.
"This research is at an early stage, but our design and fabrication techniques are scalable," Subhasish Mitra said. "With further development this architecture could lead to computing performance that is much, much greater than anything available today."
If you're attending this year's IEEE International electronic devices meeting on December 15-17, you can find this team members presenting a paper on this achievement.
Here below are some of the links from the Stanford University to learn more on their achievement:
1. carbon nano tube-based computer chip development:
2. RRAM achievement:
3. blog by the H.-S. Philip Wong explaning lot of these technologies:
Picture above : CNT wafer
Picture above : 3D structure
Source of above three images: stanford.edu
Update on this tech after meeting Subhasish Mitra in Bangalore on 7 Jan 2015:
The level of integration in the prototype they have made is equivalent to 8085 processor chip because of the limitations in the nanotechnology manufacturing equipment available at Stanford University facilities. They could only deposit three layers of metal. However he says this technology can pack a lot more processing capability compared to present silicon chips.
The major issue they are facing now with this technology is thermal instability.