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Date: 02-11-14

Jump in usage of System Verilog, UVM, and virtual in SoC design

At the recently concluded Mentor Graphics's conducted User to User (U2U) VLSI design conference held in Bangalore, Wally Rhines, CEO and Chairman of Mentor Graphics presented how EDA tools have transformed from simple gate level simulation to today's abstraction based virtual platforms. He finds from a study that most of the companies do not change EDA tools due to the availability of new features or tools, but more due to any disasters/failures in the designs. The reason is design methodologies are hard to change, substitution of new tools is risky, according to Wally Rhines. But isn't the innovation is all about risk-taking, and changing processes and methodologies for improvement. Do the smart project heads not calculate the cost of risk versus benefits? For some linear performance and speed benefits alone, moving from the Mentor's platform to Cadence, Synopsys, Aldec or some other vendor or vice-versa is not preferred, because it costs huge to buy a different set of EDA tools from different vendor. It is not just the cost of the EDA tool, but it is even more with time and human resources expences. In some aspects and market conditions, Wally Rhines is right. But when a team starts a new design with time to market pressure and have cash to take risk, then why not go for a new tool, if the tools help to complete the design in weeks rather than months. But the problem is moving the huge amount of reuse-code from one platform to other.

The top two EDA vendors Synopsys, and Cadence keep acquiring smaller EDA companies. The challenge they have now is to seamlessly integrate those newly acquired platforms into their present platforms. There are glitches and bottlenecks, VLSI engineers are facing while moving the data/design from one platform to other. The small bug is big enough to eat off the full chip design causing losses in the range of millions of US$s. A complex 28nm SoC costs anywhere in the range of 50 Million to 100 Million US$s.

Wally Rhines forecasted sooner emulation, simulation, physical testing and all the key components of VLSI design going to be integrated into a single platform. It looks like Mentor Graphics going to have an edge over Synopsys and Cadence in offering tightly integrated single environment for complete cycle of chip design. For Mentor, the task of integration is easy, because they have not acquired a large sized EDA companies recently in VLSI domain. It is a blessing in disguise for Mentor for not acquiring as much as other two leaders.

Wally Rhines and his colleague Hanns Windele, Vice President, Europe and India, Mentor Graphics shared the below other VLSI design trends at the event:
1. Full chip analog simulation is possible with speeds 5 to 10 X higher compared to traditional spice simulation.
2. Adoption of UVM is increased by 56% from 2012 to 2014.
3. System Verilog has become very common and is adopted even better, but the system C is not that strongly adopted.
4. VLSI design community in India leading in adoption
5. The simulation and emulation is going virtual, where the physical sys going to be Linux based server rather than a proprietary hardware.
6. Design reuse, is something synonym with VLSI design. It is more so with testing. There's a lot of reuse of test platforms, and test patterns are getting automated, and the chips are featuring embedded instruments.

To give you another different type of trend, the number of VLSI design engineers in Bangalore are growing rapidly, the growth pattern in someway matches Moore's Law. Though recently Moore's law not able to keep its pace on 2-D chip integration trend, talent growth in India looks to continue for some more years. So more designs are going to be Bangalored. Actually in fact the official name of Bangalore is now changed to Bengaluru, well is the word 'Bangalored' going to change! This writer could see number of young attendees not only at Mentor Graphics event but also at Synopsys' SNUG and Cadence' CDN Live going up significantly in recent years, particularly in 2014. Fresh engineers working in VLSI design houses in Bengaluru already trained in UVM and System Verilog. Thanks to free online UVM training from Aldec (Read more on that at http://www.eeherald.com/section/news/onws2013020689.html) and more such online chip design resources. Bengaluru is becoming some kind of chip verification mega resource center.

There was another keynote presentation by Pradeep Vajram, CEO of Smartplay, where he gave advise on entrepreneurship and market (including Indian chip design opportunities) we'll cover that in a separate article along with a panel discussion held on the subject of work culture.

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