It is increasingly becoming difficult to secure computer networks, mobile devices and embedded systems from unintended access. Well that is the challenge outside the semiconductor chip, there is also increase in risk of unauthorised access inside the chip too.
All these years, VLSI design engineers have focused more on increasing functions, deeper integration, power consumption, speed and such performance related tasks.
There is now a requirement of protecting complex SOC chips from security attacks. There is a need for designing VLSI circuits with multiple layers of protection. This gives an opportunity to VLSI design engineers to add the skill of "VLSI security".
Here we provide some of the available information to start with:
Companies and organisations involved in this area:
The U.S.-based Semiconductor Research Corporation (SRC) has announced the launching of a new initiative on Trustworthy and Secure Semiconductors and Systems (T3S). To know more on this visit https://www.src.org/program/grc/t3s/
There is also an event named Cryptographic Hardware and Embedded Systems , which covers security related research in hardware design.
The company called Elliptic Technologies offering SoC security design services. It has published White papers on subjects such as Crypto processor, "Secret Key and Identity Management for System-on-Chip Architects", "Symmetric Cryptographic Offload Options for SoC Designers". These white papers can be accessed at http://www.elliptictech.com/en/knowledge-center/whitepapers
There is a separate security verification tool available from Jasper called Security Path Verification App, which helps in detecting security vulnerabilities in SOC design.
Security Path Verification App verifies secure data communications and storage locations are protected from illegal access and unauthorized modifications.
Security Path Verification App enables the capture and verification of requirements that are not expressible in standard SystemVerilog Assertions (SVA), as per Jasper. It basically simulates tampering to verify the design is protected against attacks by using path sensitization technology.
Security Path Verification App allows users to specify the legal security access paths and enables users to identify potential security vulnerabilities in a SoC design by specifying functional paths between non-secure and secure areas. Jasper says this tool is already in demand and is used by leading chip companies.
Jasper has written a white paper on this subject. White Paper can be downloaded at
If you are in India and looking for ready solutions in this domain there's a company called ChaoLogix which has opened its India Engineering Center in Hyderabad, India. Anish Dhanekula is the new Director of Technology and Head of India operations.
ChaoLogix has introduced a technology called ChaoSecure to protect against side channel attacks on semiconductor chips. ChaoLogix said its ChaoSecure protects against this vulnerability by addressing the cause of the leakage at the source, rather than dealing with the symptoms. ChaoSecure is a secure standard cell library which can be integrated in your VLSI design.
Unauthorised access of content inside semiconductor Ics is done through what is called "side channels", when the time delay and power consumption pattern is collected to decode the secret keys. The most popular attack is differential power analysis (DPA). The statistical analysis is done on the power consumption pattern which can be correlated to know the password are such secret data.
1. One of the techniques suggested in a paper titled A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation" written by Kris Tiri and Ingrid Verbauwhede is: the power consumption pattern of logic gates shown constant independently of the signal transitions through a technique called Sense Amplifier Based on Logic (SABL).
This paper is available at
2. In another paper titled "Masking the Energy Behavior of DES Encryption" authors have presented how instruction set architecture of a processor chip is added with secure instructions to mask the energy differences due to key related dependent compUtations in DES encryption.
This paper is available at
To give you further information on learning methods to design security enabled SOC chip, you can find the pdf file at: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.106.5114&rep=rep1&type=pdf