Customizing is becoming important differentiator in SoC design. When OEM manufacturer buys application specific SoCs from merchant semiconductor companies, it has limited scope in adding unique performance strengths to a product. Starting with Apple many product OEMs are going for own internal VLSI design teams to add unique performance capabilities at chip level. This trend is very good news for EDA software companies where they get more number of customers. This writer recently met Lip Bu Tan, CEO, Cadence, Nimish Modi, SVP Marketing and Business development, Cadence and Anirudh Devgan, SVP Digital and Signoff group, Cadence at company's annual event CDN Live held in Bangalore recently to learn about latest in chip design. Below are the some of the VLSI design trend this writer understood after spending some time discussing with them at the event:
Moving from silicon hungry software to Silicon for app trend:
During the PC desktop period, software application developers were designing the software depending on the processor's performance which directly proportional to number of logic gates chip has. Though that trend still relevant, that is not a key driver now. Now the market requirement is directly impacting chip design. The apps what people prefer on their mobile phones or any electronic device are driving the SOC design.
Nimish said "I think what we're seeing here is application driven system design, we need to understand what vertical you're designing and value proposition of the product you are coming out. it depends on the software that drives the system requirements and system requirements drive the SOC requirement"
"if you are in telecom vertical, automotive vertical, consumer vertical, the application is reflective of the market requirements, applications and software decide the system requirements that in turn drives the SOC design"
"what we seeing is increasingly system companies are going vertical aggregated. Apple and Samsung are very good examples. They are doing the SOC development themselves, and then they are doing packaging, board, system components and software, they want to provide customised SOC for the software and then optimise all this. "
Finally PPA (power, performance and area) of the silicon is optimized to give the product a selling edge to the end-product it is powering.
FPGA in SoC:
The trend of FPGA getting into SOC is there but not as strong as other way round where hard-core blocks are getting into FPGA such as popular Zynq from Xilinx.
Power consumption continue as most important differentiator not only in mobile as well as in servers to nearly every application.
Cadence tools enhancement:
In analog VLSI design Cadence is a leader and they're trying hard to have a stronghold in digital too. They are trying to seamlessly integrate their analog tool Virtuoso with digital tool Encounter to offer mixed signal SOC design in a single platform. The unique strength of Cadence tool is they have a common database for both analog and digital design.
Availability of best mixed signal IPs from cadence is also another strength. In last 20 months Cadence acquired Cosmic Circuits, Evatronix and Tensilica whose IPs are offered to Cadence customers as a subsystem IP which combine analog front end interface and DSP. A kind of SoC chip reference designs for ODM and contract manufacturers.
Cadence growing fast in IP market. In DSP IP sales cadence is number one and in interface IP cadence is number two.
On the prospects of semiconductor industry growing at 10% and above in 2014, Lip Bu Tan was optimistic and he cautiously add the phrase "it depends" for any even bigger growth.
Pic above: Lip Bu Tan presenting key note at CDN Live India