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  Date: 21/04/2014

Triangle of collaboration for finFET success

The semiconductor industry is moving towards 3-D FinFETs more for performance rather than cost. There is going to be significant drop in leakage current. 14nm FinFET transistors are expected to increase speed performance by 20% and power consumption reduction by 35% and 15% save in space compared to 20nm planar technology. However 3D FinFET's inter-device and inter-connect behavior is not simple mathematics. The capacitance parameters of 3D FinFET is lot more complex compared to 2D.

finfet


For the production success of FinFET based 16nm SoCs, the semiconductor foundries, semiconductor equipment suppliers and EDA tool vendors are working extremely closely so that their systems work smoothly across. 14/16 nm FinFET based test chips are already out, the volume production is expected to happen any time in 2014. At the backend, the chip manufacturing technology is getting extremely complex, so much that, it is becoming increasingly difficult to scale any further by using litho techniques.

However for a VLSI design engineer, the front-end looks pretty much the same, except that the design flow/process undergoing some changes. There is a lot more automation and design checks to ensure first-time successful tape out.

FinFET and double patterning results in a lot of extraction. VLSI designers have to follow a lot more rules for placing as well as routing. A minute variation in the production process or material going to impact the IC production yield a lot. TSMC and Synopsys have a format to define and understand variations. Characterization is also important in designing FinFET based chips.

FDSOI, alternative to FinFET is also gaining importance, which is said to be less expensive but offer same performance as FinFET. STMicroelectronics is leading in FDSOI.

In a recent interaction with experts at Synopsys (Raja Subramaniam Country Director, Synopsys India, Girish Nanappa,Account Manager, Synopsys India and Suresh, IC compiler expert, Synopsys India), this writer was explained how EDA tools handle the complex analysis of huge data, so that the VLSI design engineer hardly need to know the intricacies of FinFET chip fabrication. Synopsys engineers demonstrated how Synopsys' latest software can handle complexities and bugs caused by the fin up over the plane.

Swami Venkat, Senior Director of Marketing, Design Group, Synopsys said "mobile phones are selling at higher price due to performance, basically more computing power and low power consumption, and FinFET will serve that purpose. The most important thing smart phone users look for is long battery life, where 16/14 FinFET-based chips can consume lot more less power compared to 20 nm or 28 nm planar FET chips"

Synopsys has published lot of online content on FinFET, one good article we suggest for you with title "FinFET: The Promises and the Challenges" is at
https://www.synopsys.com/COMPANY/PUBLICATIONS/SYNOPSYSINSIGHT/Pages/Art2-finfet-challenges-ip-IssQ3-12.aspx

 
          
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