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Date: 24-03-14

Self alignment helps in fabricating 16nm memory chips

CEA-Leti said it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V.

These devices useful for contactless memory applications, such as enlargement of the memory window and increased functionality. Also because of an optimised fabrication step, the devices allow better control of spacer memory gate shape and length, as per CEA Leti.

CEA Leti explains: Split-gate flash memories are made of two transistors: an access transistor and a memory transistor with a charge-trapping layer (nitride, Si nanocrystals etc.). Split-gate architectures use a low-access voltage and minimize drain current during programming, which leads to a decrease of the programming power compared to standard one-transistor NOR memories. Because programming energy decreases when memory gate length decreases, ultra-scaling is particularly relevant for contactless applications.

Memory gate width is reduced to 16nm due to poly-Si spacer formed on the sidewall of the select transistor. This approach saves chip fabricator from expensive deep node lithography steps and also solves misalignment issue.

CEA Leti further describes: The main challenges of this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length. Spacer gate has to fulfil two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping.

self alignment

TEM images of ultra-scaled self-aligned split-gate device, with a memory gate length of 16nm.

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