The Hybrid Memory Cube Consortium (HMCC) released a first draft of the new specification. The new specification supports increased data rate speeds advancing short-reach (SR) performance from 10 Gb/s, 12.5 Gb/s, and 15 Gb/s, up to 30 Gb/s. The new specification also migrates the associated channel model from SR to VSR to align with existing industry nomenclature. The ultra short-reach (USR) definition also increases performance from 10 Gb/s up to 15 Gb/s.
The first-generation specification was completed and released publicly in April 2013; several developer and adopter companies, including Altera, Xilinx, and Open-Silicon, have already begun leveraging the specification to design products and solutions that incorporate HMC technology.
"Using the HMC Gen2 specification, designers can extract even more performance from our UltraScale FPGA architecture," said Hugh Durdan, vice president of portfolio & solutions marketing at Xilinx. "Our UltraScale devices, which are currently shipping, were designed to support this specification and offer lower risk and faster time to market for high-bandwidth applications."
"The HMC Gen2 specification doubles the interface data rate, which enables system designers to more easily realize performance gains with next-generation 20nm and 14nm FPGAs and SoCs," said Patrick Dorsey, senior director of product marketing at Altera. "Our early start in delivering evaluation boards and the demonstrated interoperability between Hybrid Memory Cube devices and FPGAs enables customers to immediately start evaluating and developing HMC-based, high-performance systems."