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Date: 31-01-14

Automated setup for robust testing of USB2.0 physical layer at subsys Level

In recent past consumer electronics has continuously making highlights with the introduction of new gadgets. Every week we can see in news and magazines something new related to this segment. Manufacturers try to pack the devices with more and more features, ever increasing memory space and high speed of processors with almost no compromise on power consumption figures. While on one side all these key features give an edge to products in the competitive market, on the contrary they put serious challenges to companies in order to sustain the quality and reliability of products.

One such challenge being discussed in this article is related to ensure performance and reliability of high speed serial links e.g. universal serial bus 2.0 (USB2.0). In high-speed data transfer, serial links are becoming preferred choice of system designers and thus gaining more and more importance in the industry. While they do offer some of the great advantages viz. higher speed, low power, lesser cabling, easy connectivity; they also demand many system level constraints to be carefully addressed.

CHALLENGES:
One of the major concerns with High-Speed serial links is noise susceptibility, which can affect the performance very badly. Even if a single bit is corrupted during transmission, entire packet can be turned down by the receiver and information is lost. There may be carefully devised methods established at
protocol level to take care of such errors, for example in USB2.0, retransmission of packets is initiated if no acknowledgement token is received back from the other end. While these methods can ensure smooth functionality of applications but such hiccups definitely bring down the throughput of communication link.

Also there is a limit till which the errors can be handled by protocol, and after that limit is reached, system can be reset and may not respond, halting the entire data transfer. Hence a system with high speed link which is more noise susceptible can demonstrate smooth functionality to user but at the cost of reduced
throughput and in extreme cases it can also result in system failure.

These performance issues can easily go undetected in some cases if system is not characterized to detect such bit corruptions while data transfer is done at application level. Noise susceptibility can be more at a particular Process, Voltage and Temperature (PVT) condition, which may not be tested during normal course of testing. Also occurrence of worst case random noise cannot be guaranteed unless large amount of data transfer is done for a long time.

The above requirements clearly escalate the need of a setup which detects the protocol errors at different PVT conditions with huge and worst case data volumes during tests, records and plots errors and thus prevents any system failure or reduced throughput in the field.

Read the full article at http://www.eeherald.com/section/design-guide/usb2-physical-layer-st.pdf

By Pratik Damle, Gaurav Mathur, Ritesh Mishra, Rajan Sharma and Rakesh Malik, STMicroelectronics India

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