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Date: 16-01-14

VLSI Design: Hack-free semiconductor IC becoming necessity

While securing software from hackers is important, but the real weak point lies in the semiconductor chips which runs the software. However robust is the software, if the processor whether its high end server or a embedded microcontroller has some loopholes, security of the systems can be breached through physical silicon. In the present world where everything going to be connected to Internet, designing robust secure semiconductor IC is becoming more important for VLSI design engineers.

The U.S.-based Semiconductor Research Corporation (SRC) has announced the launching of a new initiative on Trustworthy and Secure Semiconductors and Systems (T3S).

The goal of T3S is to develop strategies and tools for the design and manufacture of chips and systems that are reliable, trustworthy and secure. This includes increasing resistance and resilience to attack or tampering and improving the ability to provide authentication throughout the supply chain or in the field.

Initial T3S industry participants include Advanced Micro Devices, Freescale, Intel Corporation and Mentor Graphics. The initiative is also open to companies that are not already members of SRC. NSF is the first federal partner.

“Semiconductor-based hardware is at the heart of today’s interconnected and intelligent systems — from the GPS in your car and your phone to transportation, financial, energy and other critical infrastructure systems,” said SRC President Larry Sumney. “As we increasingly depend upon these systems, their trustworthiness, security and reliability are more important than ever.”

SRC says today design and manufacture of semiconductor circuits and systems includes extensive verification and testing to ensure the final product does what it is intended to do. Similar approaches are needed to provide assurance that the product does not allow unwanted functionality, access or control.

"This includes strategies at all stages, from architecture through manufacture and throughout the lifecycle of the product,” said Celia Merzbacher, SRC Vice President for Innovative Partnerships. “Being able to assure that a product performs as designed and does nothing else is what Trustworthy and Secure Semiconductors and Systems research is about.”

SRC also highlights the need of security assurance of various silicon IP components developed by different teams across the world and also used from third-party off-the-shelf silicon IP suppliers.

“The increase in complexity and fragmented supply chain compounds the need for focused research,” said Keith Marzullo, director of NSF’s Division of Computer and Network Systems. “The academic research community is well-suited to perform the fundamental research that will lead to robust technological solutions. And the collaboration between NSF and SRC will provide pathways for results to efficiently move into practical use.”

NSF-SRC joint funding opportunity on STARSS seeks research proposals in the following areas:
Architecture and design;
Security properties, principles and metrics;
Current and future threat assessment;
Security verification and analysis;
Tools and frameworks for implementing security in design; and
Authentication and attestation.

To make SOC design more secure, various techniques have evolved and has become an interesting research area. Below we list some of the well-known techniques adopted in VLSI chip design:

The most basic thing to secure chip is to shield the device to maximum level from electromagnetic interference ( both emission and reception). No electronic signal should come out of the chip with open data.

No sensitive data should be stored in the register or cache after the completion of processing such data. So protection of registers and other storage memory areas is important.

There are various methods available to deceive the hacker from getting the data through simple power analysis or differential power analysis techniques. Sending dummy data along with the real data is one technique.

There is also a separate security verification tool available from Jasper called Security Path Verification App, which helps in detecting security vulnerabilities in SOC design.

Security Path Verification App verifies secure data communications and storage locations are protected from illegal access and unauthorized modifications.
Security Path Verification App enables the capture and verification of requirements that are not expressible in standard SystemVerilog Assertions (SVA), as per Jasper. It basically simulates tampering to verify the design is protected against attacks by using path sensitization technology.

Security Path Verification App allows users to specify the legal security access paths and enables users to identify potential security vulnerabilities in a SoC design by specifying functional paths between non-secure and secure areas. Jasper says this tool is already in demand and is used by leading chip companies.

To give you further information on learning methods to design security enabled SOC chip, you can find the pdf file at: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.106.5114&rep=rep1&type=pdf

Jasper has written a white paper on this subject. White Paper can be downloaded at
http://www.jasper-da.com/resource-library/technical-white-papers

There is also an event named Cryptographic Hardware and Embedded Systems , which covers security related research in hardware design.

The company called Elliptic Technologies offering SoC security design services. It has published White papers on subjects such as Crypto processor, "Secret Key and Identity Management for System-on-Chip Architects", "Symmetric Cryptographic Offload Options for SoC Designers". These white papers can be accessed at http://www.elliptictech.com/en/knowledge-center/whitepapers

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