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Date: 29-10-13

eASIC and CST reduce multi-level PCB package design time by 5x

eASIC and Computer Simulation Technology (CST) have teamed up to significantly reduce multi-level PCB package design and simulation. The solution will be presented at the Industry Spotlight session at EPEPS 2013 (Electrical Performance of Electronic Packaging and Systems) on October 28th.

The solution focuses on PCB package co-design and provides accurate, effective decomposition and segmentation modeling techniques for PCB package systems co-simulation. The techniques allow accurate accounting of all discontinuities present at the package interface while saving significant computational effort and resources. The methodologies reduce co-simulation time by up to 5X when compared to the full model simulation, while preserving higher accuracy when compared to traditional partitioning practices.

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