At the recently concluded VLSI and PCB design event CDN India live 2013, Lip Bu Tan, President and Chief Executive Officer of Cadence Design Systems highlighted the latest trends in electronics such as big data, Internet of things, social media, mobility, and cloud computing. The hot products highlighted by Lip Bu includes Smart watch and wearable electronics, 4K displays, e-glass and electric cars.
Lib Bu Tan shared to viewers his analysis of how 8 million servers, 50 million cars, 100 million tablets, billions of mobile phones sending and receiving huge quantity of data across networks worldover. Processing this huge amount of data is called big data analysis, whose size is expected soon in the range of zettabytes. While sharing the trend of growing big data movement between servers and clients, now which also includes Internet connected home appliances and smart systems, Lip Bu said chip design software from Cadence can handle 2.3 billion logic gates. With the data growing bigger and bigger, the functions inside the chips are growing smaller and smaller by the physical size they occupy. He talked about deep nm trends such as 3-D semiconductor fabrication, multiple patterning and the most important, the finFET.
Lip Bu Tan is very hopeful of Indian entrepreneurs in technology domain, he had forecasted next big technology innovator in the world is going to come from India. Lip Bu, also as a well-known venture capitalist set-aside millions of dollars to invest in Indian start-ups. In semiconductor domain, He expects another 50 start-ups to come up in India. Cadence had recently acquired, a successful analog and mixed signal IC design Indian start-up called Cosmic Circuits, in which the Lip Bu Tan was investor.
Tom Beckley, Senior Vice President Custom IC and PCB group of cadence design Systems also presented a keynote sharing the latest trends in analog and mixed signal design and also explained the benefits of new highspeed Fast Spice simulator from Cadence. Tom said the growing video content and wireless sensor data is making analog design more complex. A good example he quoted is self driving car, which receive and send gigabytes of data across its sensor networks. He suggests to see analog path in digital context while designing complex SoCs.
Tom Beckley and John Pierce, Director Product Marketing custom IC and PCB group of cadence design Systems have explained to this writer about the challenges in moving the design from bigger node to most advanced node such as 14 nm. Below is what this writer has understood from their explanation on challenges in moving to advanced nodes:
The challenges VLSI design engineers face when moving the design from 65/45 nm to 32/28 nm is quite different from the challenges they face when they move into 16/14 nm. At 16/14nm nodes finFET comes into the picture, the finFET and the increase in parasitics demand some fundamental change in the design. Example, there are more number of layout dependent paths, increased design corners, power domains. Also, like any other node move, 28 to14 nm too have a lot of silicon available, a lot more analog and mixed signals, a lot more memory and a lot more compliance to standards.
Irrespective of the advancement of EDA tools, the design talent need to be better and also has to be bigger to complete chip design at 16/14 nm. The finFET based chip design require 2/3x of more VLSI design engineers compared to a larger node non finFET -based design. Even if designer retain same functionality of 28/32 nm, the move to 16/14 nm create a lot more design challenges in layout, and power domain. Verification work also increase.
At 1x nodes, the communication between VLSI design engineers and semiconductor foundries increases much more. Close working with the semiconductor fab engineers gains more importance at 1x nodes. At 1x node with EUV and multiple patterning are necessary, which requires lot of information exchange between engineers of the Fab and the chip designers.
Having latest version of EDA tools is crucial. Not only for advanced nodes even for doing 90 nm/65 nm, which many people are still designing, the latest EDA tools makes a life of VLSI design engineers a lot more easier.
Jaswinder Ahuja, Corporate Vice-President and Managing Director of Cadence India said this year's event has received overwhelming response with excellent papers. He also said to this writer they are planning to offer cloud-based online VLSI design tools to engineering colleges for designing chips without having the complex software on their computers.