Electronics Engineering Herald                  ADVT
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New

News

  Date: 07/10/2013

65.2% of NAND flash to be produced using 3-D process by 2017

Semiconductor memory manufacturers are going faster in three-dimensional fabrication of semiconductor wafers to increase the memory density.

IHS has reported by 2017, nearly 65.2 percent of all NAND memory chips shipped worldwide going to be produced using 3-D manufacturing processes, up from less than 1 percent in 2013.

IHS estimates the share of the overall NAND market accounted for by 3-D technology is set to jump to 5.2 percent in 2014, and then surge to 30.2 percent of total flash memory shipments in 2015. In 2016, 3-D NAND will enlarge its market share to 49.8 percent, as for IHS. The figure below provides more data on that.

NAND


“There’s widespread agreement that just one or two generations may be left before NAND flash made using conventional planar semiconductor technology reaches its theoretical limit,” said Dee Robinson, senior analyst, memory and storage for IHS. “As lithographies shrink further, performance and reliability may become too degraded for NAND to be used in anything but the very lowest-cost consumer products. Because NAND suppliers are compelled to continue building products with higher densities and lower prices, they will migrate to 3-D manufacturing quickly in the coming years.”

IHS shares these below further details of its latest study on three-dimensional fabrication:

A major factor driving NAND makers to keep improving their products is demand from products like media tablets and smartphones. These devices are demanding higher capacity and less expensive storage of content, including pictures, music and video.

Historically, NAND flash makers have employed miniaturization to increase the capacity and reduce the costs of their products. Miniaturization is the process of shrinking the NAND flash cells with each successive technology generation, allowing suppliers to fit more bits on each silicon wafer.

With 3-D technology, the emphasis shifts away from miniaturization and toward increasing density by layering NAND flash cells on top of each other. This will be the most cost-effective way of pushing NAND to the next level because most of the existing manufacturing equipment can continue to be used, minimizing expenses while maximizing return on investment.

Samsung and SK Hynix, the biggest players in the global memory trade, announced their initiatives in 3-D NAND in August during the Flash Memory Summit in Santa Clara, Calif.

Samsung said commercial production of V-NAND, the company’s name for its 3-D flash memory products, started during the second quarter. The end product will be a V-NAND-based solid-state drive, in 480- and 960-gigabyte densities, initially targeting the enterprise market. V-NAND, Samsung says, will be more reliable than 1x-nanometer NAND, consume less power and also deliver higher performance in sequential as well as random writes.

The cost differential between a V-NAND solid-state drive and one powered by traditional flash memory will be quite large, IHS expects, which would explain why Samsung is aiming the product first at the enterprise market.

Samsung archrival SK Hynix is also planning to manufacture 3-D NAND; its initial 3-D product will be very similar to Samsung’s V-NAND, to be available in 128-gigabyte capacity. But this is part of a two-pronged approach, as the company is also sampling a 16-nanometer product.

While both Samsung and SK Hynix have previously mentioned internal development of 3-D NAND, the timeline for production has moved faster than expected, and the accelerated pace is much quicker than many in the industry had anticipated.

Other memory manufacturers, however, have decided to continue with planar NAND for at least one more generation, pushing any 3-D plans to a later date. In this group are makers like SanDisk of California, Idaho-based Micron Technology and Toshiba of Japan.

All told, initial production of 3-D NAND will be limited, and failure analysis will be difficult because of the multilevel structure of the device. Still, an initial ramp-up of higher-performing products into the enterprise segment will enable suppliers to generate margins and allow processes to mature, IHS believes, even though it may be some time before 3-D contributes meaningfully to overall industry bit growth.

At any rate, the 3-D race for NAND has already begun, solidifying the timeline for the new technology. NAND suppliers that have yet to address the change are likely to feel pressure to innovate as a result.
Author: Srinivasa Reddy N
Header ad

 
          
ADVT
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2012 Electronics Engineering Herald