Aldec is organizing C language based chip design webinar on SEP 12, 2013. Webinar named "CyberWorkBench: C-based High Level Synthesis and Verification (Europe)" is scheduled at 3:00 PM - 4:00 PM CEST time.
CyberWorkbench is developed by NEC for designing ASIC and FPGA chips. CyberWorkbench can be used for behavioral synthesizer, simulator and formal verifier tasks.
For more info visit: http://www.aldec.com/en/events/register/291