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  Date: 25/08/2013

New materials, processes developed for SiP assembly

Infineon has announced, group of companies in Europe working on building solutions for System in Package (SiP) assembly of electronic components have successfully come out with solutions.

To build electronic subsystems, the process of traditional printed circuit assembly is time-consuming, space consuming and also expensive. Best idea is to put most of the functions on the silicon chip itself. But there is a technology limitation for integrating sensors, RF, LEDs and any such non-silicon-based electronic components which includes passive components such as resistor capacitor and inductor on the single semiconductor IC. So the better option is to place all these different types of components one next to the other or one above the other or it can be a combination of both vertical and horizontal integration. These components are bonded and wired together using different materials, different processes, compared to the way they are connected on a printed circuit board. The idea here is to use less human interface in building the subsystem and to use semiconductor packaging equipments/machines for multi-device assembly.

Infineon and its partners have successfully developed new materials, processes, test procedures for building system in package devices, what is called as embedded system in package (ESiP). Infineon said they have developed SiP, which is more compact and reliable with simplified analysis and tests. Under management of Infineon Technologies and with 40 research partners, ESiP was funded by public authorities of nine European countries and the ENIAC Joint Undertaking.

SiP devices target products such as electric vehicles, industrial applications, medical equipment and communications technology.

Infineon and its research partners said to have proved the feasibility and reliability of the new production processes with more than 20 different test vehicles. They have developed new test flows, probe stations and probe adapters were developed for SiP.

“The successful ESiP research enhances Europe's position in the development and manufacture of miniaturized microelectronics systems,” says Dr. Klaus Pressel, ESiP project head and responsible for international cooperation on assembly and packaging solutions at Infineon Technologies AG. “With the ESiP findings we will be able to further miniaturize and improve microelectronic systems. We have developed new manufacturing processes and materials for SiP solutions along with methods for testing them, running a failure analysis on them and evaluating their reliability.”

The other members in this project include Fraunhofer-Gesellschaft, Cascade Microtech GmbH, Feinmetall GmbH, Infineon Technologies AG, InfraTec GmbH, PVA TePla Analytical Systems GmbH, Siemens AG and Team Nanotec GmbH.

More information on this project can be found at: www.eniac.eu/web/downloads/projectprofiles/call2_eniac_esip.PDF

To share with you the type of innovation happening in multidevice IC packaging, here is announcement from STAT ChipPAC, where it has announced reduction in Package-on-Package (PoP) height with its ultra thin embedded Wafer Level Ball Grid Array (eWLB) technology. The logic-processor silicon-die and semiconductor memory-die are stacked one over the other, so that it saves space on the printed circuit board of mobile phones but these PoP devices need to be thin to support slim phone design.

 
          
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