Taiwan's semiconductor packaging industry to benefit from 2.5/3D technologies
SEMI says design tools, manufacturing, packaging and testing solutions for 2.5D-IC process are available this year, and the most important issue is how to improve its throughput to enable 2.5D-IC mass production in 2014.
Taiwan is said to benefit from the growth of three-dimensional semiconductor fabrication technologies. Taiwan with a market share of higher than 50%, is home to leading packaging and testing companies such as ASE, SPIL, PTI, and ChipMOS. Amkor and STATS ChipPAC also have semiconductor packaging plants in Taiwan.
SEMI quotes a forecast from ITIS, where it says the Taiwan IC packaging and testing industry will significantly grow by 15.5 percent, and the driving force is from growing demands from the networking, graphics, wireless, computing device, and mobile handsets markets.
SEMI also shares another forecast from Yole Développement, where it says the market value of all the devices using TSV packaged in 3D in the 3D-IC or 3D-WLCSP platforms (CMOS image sensors, Ambient Light Sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7 billion in 2011. By 2017, the market value is said to reach almost $40 billion, representing 9 percent of the total semiconductor value.
One more research point shared by SEMI is: TechNavio analysts forecasted the global 3D-IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. One of the key factors contributing to this market growth is the huge demand for memory-enhanced applications, according to SEMI. SEMI says ASE and SPIL to expand their capex for increase bumping, flip chip and copper wire bonding capacity. ASE has set aside a capex budget of US$ 0.7 billion and SPIL of US$ 498.9 million for 2013, as per SEMI.
"While 2.5D with TSV have been widely adopted in CMOS sensors and MEMS, affordable stacked memory is not yet available. In addition, many companies are also looking at alternatives to silicon interposers, such as glass interposers, to bring the price down. So, even 2.5D has been delayed and questions remain about its configuration at high volume." said Terry Tsao, president of SEMI Taiwan. "For heterogeneous integration of memory and logic, the industry still needs design tools, thermal solutions, continued work on wafer bonding and de-bonding, and accepted test methodologies, to name a few requirements. The SIP Global Summit will explore these barriers and opportunities to accelerate 3D IC's beyond today's applications.”
SEMI said it will hold the SiP Global Summit 2013 from September 5-6 under the auspices of SEMI’s Taiwan Packaging and Testing Committee as well as major international enterprises and research organizations.
This two-day SiP Global Summit 2013 (www.SiPGlobalSummit.org) will consist of two major forums: 3D-IC Technology and Embedded Technology. Participants in the summit will include TSMC, ASE, SPIL, Unimicron, Amkor, Qualcomm, STATS ChipPAC, research institutes and market research organizations including Fraunhofer IZM and Industrial Technology Research Institute (ITRI).
2.5 D is a kind of chip stacking technology, where multiple wafers or placed over silicon interposer, which acts as an interconnect. Where as in 3D, it is a pure vertical integration of chips such as processor, memory, and MEMS.