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Date: 10-07-13

Dow Corning joins imec to help in researching 3D bonding of wafers

Silicone expert Dow Corning is joining with imec in 3D packaging of semiconductor wafers. Dow Corning to explore its temporary bonding CMOS-compatible solution for 3D Through-Silicon-Via (TSV) semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.

Imec explains: One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its Temporary Bonding Solution, aims at simple processing using a bi-layer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.

“This move is a natural and strategic step for Dow Corning and imec, as we both believe collaborative innovation is as critical to industry leadership as native expertise,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning. “Our access to imec’s world-class resources and expertise will not only help us further refine our unique temporary bonding solution, it will allow imec to leverage that solution to advance integration of the 3D IC packaging process that they’ve been developing for years.”

“Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research. As one of the semiconductor industry’s most proven pioneers in advanced silicone-based solutions, Dow Corning brings valuable materials and processing expertise to imec’s global network of innovators – as well as a key enabling technology for TSV fabrication,” said Eric Beyne, program director 3D System Integration at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3D integration, and help ensure compatibility of the proposed thin wafer carrier solution with advanced, sub-10-nanometer CMOS device technologies.”

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