TSMC supports Cadence' Virtuoso for design and verification of Ips
Cadence Design Systems has announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own cutting-edge IP. TSMC has also extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers. The new PDKs support features within the Virtuoso 12.1 platform, such as auto-alignment, automatic handling of complex rules during abutment, chaining devices, support of color-aware layout, and advanced routing.
“We have continued our major investments in advancing the Virtuoso platform to address the ever mounting design challenges. We worked closely with TSMC and our customers to enhance and deliver on advanced node and mainstream design requirements,” said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “The high-quality native SKILL-based PDKs are key to powering up the Virtuoso methodologies to their full potential.”
“We have a long-term partnership with Cadence on the Virtuoso platform,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The extension of SKILL-based PDK development to 16 nanometers allows us to better address customers’ needs in custom design of advanced technologies.”
Cadence Design Systems is offering in-design electrical verification capability in its Virtuoso Layout Suite for Electrically Aware Design (EAD). VLSI design teams can monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the original design intent. Cadence claims Virtuoso Layout Suite EAD allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance.
Custom IC design engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices – or “over-design” – that can negatively impact a chip’s performance and area, suggests Cadence.