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Date: 04-06-13

Jasper and Duolog offering integrated chip design flows for IP/SoC design

Jasper Design Automation and Duolog Technologies offering integrated chip design flows to enable IP/SoC development teams to deliver qualified, integration-ready IP and SoC assembly that is seamlessly verified using formal verification methods. “ARM delivers packaged and verified IP that enables our customers to meet their design targets with reduced risk,” said John Goodenough, vice president of Design Technology and Automation, ARM. “Duolog and Jasper have been valued partners providing IP integration and verification tools and flows for these mission-critical processes. The new, integrated flows from the two companies should both increase productivity and quality for us and for our customers.” The partnership will initially deliver two flows. The first will focus on the capture and verification of register metadata, combining Duolog’s Socrates Bitwise register management tool with the JasperGold Control and Status Register (JG-CSR) Verification App. The flow will enable IP designers to verify both executable specifications and RTL for consistency and completeness. The second flow leverages Duolog’s Socrates Weaver SoC integration tool and the JasperGold Connectivity Verification App (JG-CONN). This flow will enable SoC design teams to assemble, construct and exhaustively verify a complete SoC integration, including temporal and conditional connections, as well as multiplexed IO connections. Duolog’s and Jasper’s solutions utilize the IEEE1685 IP-XACT standard as a robust data exchange format to seamlessly exchange metadata among the different tools and enable these joint flows. With ARM IP being packaged using IP-XACT, Duolog and Jasper’s solutions are 100% interoperable with ARM IP enabling a fully automated methodology and flow. “Getting from a specification to complete and verified SoC integration is a tedious, repetitive cycle of modification and verification,” said Norman Walsh, COO of Duolog. “The Duolog/Jasper partnership will transform this into a highly effective cycle of continuous integration and verification that will have a significant positive impact on both SoC quality and time-to-market.” “The two companies’ solutions are more than complementary — they are an ideal fit,” said Oz Levia, Vice President of Marketing and Business Development, Jasper Design Automation. “The integrated design flow is very intuitive, from black-box system specifications, through design capture and integration, to verification. And the Duolog/Jasper partnership will assure ongoing compatibility of our tools and technology roadmaps.” Availability: The new flows are available now.

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