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Date: 30-05-13

Papers by Rambus engineer on 3D semiconductor signal and power integrity

Are you interested in knowing memory interface solutions for 3D Semiconductor technology from Rambus! At the Electronic Components Technologies Conference (ECTC) 2013, the industry’s premier international packaging, components, and microelectronics systems technology conference, Rambus engineers and inventors will present three papers on 3D IC signal and power integrity, and characterization of advanced low-power memory interfaces.

Tuesday, May 28, 2013
3:30 p.m.
Title: “Signal and Power Integrity Analysis of a 256GB/s Double-Sided IC Package with a Memory Controller and 3D Stacked DRAM”
Wendem Beyene, Hai Lan, Scott Best, David Secker, Don Mullen, Ming Li, and Tom Giovannini – Rambus Inc.

Thursday, May 30, 2013
2:20 p.m.
Title: “Analysis of Power Integrity and Its Jitter Impact in a 4.3Gbps Low-Power Memory Interface”
Hai Lan, Xinhai Jiang, and Jihong Ren – Rambus Inc.

Friday, May 31, 2013
8:50 a.m.
Title: “Characterization of a Low-Power, 6.4 Gbps DDR DIMM Memory Interface System”
Ravi Kollipara, Shuh Chang, Chris Madden, Hai Lan, Liji Gopalakrishnan, Scott Best, Yi Lu, Sanath Bangalore, Ganapathy Kumar, Pravin Kumar Venkatesan, Kapil Vyas, Kambiz Kaviani, Michael Bucher, Lei Luo, and Kashinath Prabhu – Rambus Inc.

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