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Date: 24-05-13

Demo on formal technology use in VLSI design and verification at DAC 2013

VLSI chip design services company Oski Technology to demonstrate Oski Formal Sign-off Methodology during the 50th Design Automation Conference (DAC) in Booth #718 on Monday, June 3, through Wednesday, June 5, from 9 a.m. until 6 p.m. daily at the Austin Convention Center in Austin, Texas.

The demonstration will showcase the benefits of applying custom Abstraction Models during formal analysis to reach deeper search depth and achieve faster proof. It will show how the Oski Formal Methodology, coupled with end-to-end checkers and formal coverage, makes formal sign-off possible.

Oski Technology to launch its “Decoding Formal” video series where Vigyan Singhal, Oski’s chief executive officer, shares tips and secrets on how to make the best use of formal technology in system-on-chip (SoC) design and verification. Videos will be shown hourly, starting at 9:30 a.m. Topics include:
· How to formally verify — and reuse — highly configurable IP designs
· How to know when a formal testbench is complete
· How to achieve early formal convergence with Oski Abstraction Models

DAC attendees are invited to an Oski "Decoding Formal" reception and compete to win prizes in the live “Decoding Formal” trivia challenge competition. The two events will be held Monday, June 3, and Tuesday, June 4, from 5:15 p.m. until 6:00 p.m. in Booth #718. Light refreshments will be served. Alternatively, the challenge can be played online at: https://www.surveymonkey.com/s/DecodingFormal

Singhal will offer a look at Sequential Equivalence Verification at the Jasper Design Automation (www.jasper-da.com) Booth #2346 Monday, June 3, at 10 a.m. and Wednesday, June 5, at 1:30p.m. He will present “Myths and Facts about Formal” during the Mentor Verification Academy (https://verificationacademy.com) in Booth #1215 Tuesday, June 4, at 4 p.m.
For more information about Oski Technology, go to: www.oskitech.com.

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