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Date: 03-03-13

Verilog HDL parser expert Verific reports revenue growth of 20% in 2012

SystemVerilog, Verilog and VHDL parser tool provider Verific Design Automation has reported it has ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.

“Much of our business in 2012 came as a result of our reputation for quality, reliable software and excellent customer service, the hallmarks of our corporate culture,” says Michiel Ligthart, Verific’s president and chief operating officer. “EDA developers continue to select our parsers so that they can focus on their core competencies and get their products to market more efficiently.”

In 2012, Verific signed six new licensed customers in a mix that includes both electronic design automation (EDA) companies and integrated device manufacturers (IDMs). Several existing customers added further software to their existing product mix.

The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

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