Semiconductor packaging expert STATS ChipPAC and the semiconductor foundry service provider United Microelectronics Corporation have demonstrated TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. I/O memory test chip stacked over TSV-embedded 28nm processor test chip is assessed for package-level reliability. This demonstration is to tell the market that reliable 3D IC manufacturing is offered jointly by UMC’s foundry and STATS ChipPAC’s packaging services.
”The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models.” said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC, “The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner’s robust, leading-edge TSV and front-end-of-line (FEOL) process technologies in a complementary platform with an Outsourced Semiconductor Assembly and Test (OSAT) service provider with innovative engineering excellence to seamlessly integrate mid-end-of-line (MEOL) and back-end-of-line (BEOL) 3D IC processes. We are pleased with UMC’s commitment to this role and look forward to future collaborations. The results are a proven solution platform that will enable customers to capitalize on new market opportunities.”
S.C. Chien, vice president of Advanced Technology Development at UMC, said, “We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models.”
The release states "under the 3DIC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking. "