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Date: 03-03-13

Imec and Cadence tested automated DFT for 3D Memory-on-Logic Ics

imec and Cadence Design Systems have announced that they together developed, implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in 3D semiconductor IC packaging of DRAM and logic silicon dies. Using Cadence Encounter tool from Cadence the team has verified an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DRAM.

Imec explains the design of the test chip is an interposer-based 3D stacked chip which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The silicon area of the additional DFT wrapper is negligible compared to the total logic die size (

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