MoSys has announced that Renesas Electronics to support the GigaChip Interface in its Networking ASIC business. The GigaChip Alliance was founded by MoSys, the other promoters include Altera, LSI and Xilinx. The GigaChip Interface is a short range low power serial-wire high-speed interface using differential SerDes technology. The GigaChip Alliance says 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times. Current implementations built with compatible CEI-11G or XFI SerDes electrical transport standards deliver up to 144Gbps of full duplex data throughput using 16 serdes lanes when running at a 10G rate. The speciality of GCI protocol is high transport efficiency, even for small payloads.