SEMI today announced that team members at Intel Corporation — Mark Bohr, Robert Chau, Suman Datta, Mark Doczy, Brian Doyle, Tahir Ghani, Jack Kavalieros, Matthew Metz, and Kaizad Mistry — are recipients of the 2012 SEMI Award for North America. The Intel team was honored for their contribution to the first development, integration and introduction of a successful high-k dielectric and metal electrode gate stack for CMOS IC production, first implemented at the 45nm node in 2007. Dr. Robert Chau accepted the SEMI Award on behalf of his team during a banquet at the 2013 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.
The successful introduction of a high-k/metal gate structure in commercial IC devices, aided by support from SEMI member companies with development of appropriate materials, processes and production tools, was a critically important milestone and continues to be in use throughout the IC industry for advanced planar and finFET-like CMOS transistors.
Team members include:
Mark Bohr, senior fellow and director of Process Architecture and Integration, Logic Technology Development, Intel
Robert Chau, senior fellow and director of Transistor Research and Nanotechnology, Components Research, Intel
Suman Datta, professor, Electrical Engineering, Pennsylvania State University*
Mark Doczy, senior engineer in Advanced Transistor and Nanotechnology Group, Components Research, Intel
Brian Doyle, principal engineer in Advanced Transistor and Nanotechnology Group, Components Research, Intel
Tahir Ghani, fellow and director of Transistor Technology and Integration, Logic Technology Development, Intel
Jack Kavalieros, principal engineer in Advanced Transistor and Nanotechnology Group, Components Research, Intel
Matthew Metz, senior engineer in Advanced Transistor and Nanotechnology Group, Components Research, Intel
Kaizad Mistry, vice president and director of Logic Technology Integration, Logic Technology Development, Intel
To keep on the Moore's Law curve, transistor size had to be cut in half every 24 months. However, one critical part of the transistor could not shrink anymore — the thin layer of silicon dioxide (SiO2) insulation that electrically isolates the transistor's gate from the channel through which current flows when the transistor is on. That insulating layer has shrunk with each new generation, but gate leakage currents increased with each shrink. By 2007, these leakage currents were becoming too large and the thickness could no longer decrease. Intel and other chipmakers could not shave off even a fraction of a nanometer more. Without a significant innovation, the semiconductor industry faced the end of the Moore's Law era. The team’s development, integration and introduction of a successful high-k dielectric and metal electrode gate stack for CMOS IC production — first implemented at the 45nm node in 2007 — allowed the industry to perpetuate Moore’s Law. The decrease in power, decrease in size and increase in performance enabled by this innovation changed the future of the IC industry.
“The invention of the high-k plus metal gate transistors was an important breakthrough,” said Denny McGuirk, president and CEO of SEMI. “The Intel team pioneered a new era of transistor design based on novel device architecture and advanced materials development.”
“Against all odds, the Intel team tackled a problem that threatened Moore’s Law, and succeeded,” said Bill Bottoms, chairman of the SEMI Award Advisory Committee. “The oxide layer was so thin that individual atoms of thickness had to be counted, so the industry was at a crossroads. The Intel team identified a gate dielectric material as a replacement for SiO2 that reduced gate leakage and moved the industry forward.”
News Source: www.semi.org