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  Date: 12/07/2012

IP subsystem use: Major trend in SoC design

When the SoC VLSI designer is faced with the challenge of designing complex 28nm/20nm design with in shortest time frame, the mantra for chip-designer is design-reuse. Either reuse their own proprietary IPs and 3rd party IPs. Though the VLSI engineer gets lots of 3rd party IPs, the other challenge is bug-free integration of VLSI functional blocks. Many IP vendors offering ready solution for this problem. They are not just offering IP pieces but IP subsystem itself, that too a validated IP blocks. They are checked for various physical layer bugs and also for interface issues.

This trend of using validated silicon IP block in the form of sub-system is growing big now. Say, per example a tablet PC built using ARM Processor core would need to go for another version based on MIPS processor core. The rest of the interface blocks including graphics core remains same. Here the chip designers leverage validated subsystem IP blocks to quickly replace only selected blocks in his design.

Since 2010, during which 32nm node started getting commercialized, the IP subsystem market is growing in double-digit rate and is also estimated that a near-triple digit growth in 2011 and 2012.

Leading IP vendors offering pre-verified hardware and software subsystem mainly for mass consuming applications. Synopsys says configuration of its complete audio IP subsystem can be done in hours instead of weeks.

“With the average number of IP blocks in an SoC expected to reach close to 120 by 2014, designers need solutions that help them reduce the effort needed to integrate the IP and manage the complexity of those blocks,” said Rich Wawrzyniak, senior market analyst at Semico Research Corporation. “With complete, pre-verified IP subsystems, which include the hardware as well as the software that goes around the IP, designers can solve their design issues at the chip-level rather than the individual block level.”

It is also said by many experts that 3rd party IP share is increased to a range 60% in a SoC chip. It is only expected to increase further in coming years.
Author: Srinivasa Reddy N
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