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  Date: 26/06/2012

SEMATECH experts to talk on III-V semiconductor and 3D ICs at SEMICON West 2012

SEMATECH and International SEMATECH Manufacturing Initiative (ISMI) to present a variety of technology solutions and manufacturing methods through a series of lectures and workshop sessions from July 10–12 at SEMICON West in San Francisco, CA.

SEMATECH and ISMI experts are to report their latest advances in new materials and device structures and lithography with a special focus on addressing important opportunities and challenges in 3D interconnect technology.

“Every year the semiconductor industry continues to make significant advances for continued scaling of semiconductor technologies,” said Dan Armbrust, president and CEO, SEMATECH. “At this year’s conference, we will continue to address industry needs by showing novel approaches and practical solutions to some of the industry’s most complex technology challenges. We look forward to sharing our technical knowledge and best practices to help drive our industry forward.”

SEMATECH experts scheduled to speak on the SEMICON West TechXPOT Stage, in the South Hall of the Moscone Center, includes:
1. Raj Jammy, SEMATECH’s vice president of Materials and Emerging Technologies, “Emerging Semiconductor Technologies – a Heterogeneous World on Silicon,” July 10 at 10:30 a.m.
2. Paul Kirsch, SEMATECH’s director of Front End Processes, “Challenges and Opportunities in High Mobility Ge/III-V Channels and Devices,” July 10 at 2:10 p.m.
3. Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Remaining Challenges to HVM Introduction,” July 11 at 10:30 a.m.
4. Bill Ross, ISMI’s project manager, “Tool Obsolescence and Sustaining Legacy Manufacturing,” July 11 at 1:40 p.m.

SEMATECH to host public workshops at the San Francisco Marriott Marquis during SEMICON West:
1. Participants to identify the challenges of electro-static discharge in 2.5D and 3D ICs and explore how fabless companies, IDMs, foundries, and OSATs address present concerns at both the design and manufacturing levels at the ESD Challenges for 3D ICs Workshop on July 10 at 8:00 a.m.
2. Equipment suppliers to share their plans on how new and existing wafer metrology techniques can be used, modified, or enhanced to measure and improve 3D interconnect processes at SEMATECH's 3D Metrology Workshop on July 11 at 7:30 a.m.
3. A half-day preview of this year’s International Technology Roadmap for Semiconductors to be offered at the Summer ITRS Public Conference on July 12 at the Moscone Center, TechXPOT stages.

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