Date:7th June 2012

IP core for interfacing 3D integrated semiconductor memory devices

VLSI design services company Open-Silicon has made available Hybrid Memory Cube (HMC) controller IP core for interfacing semiconductor memory devices such as flash, DRAM and SRAM on 3 dimensionally built Hybrid Memory Cube (HMC). HMC controller IP core is based in high-bandwidth serial protocols derived from Open-Silicon's Interlaken controller IP core.

"The mission of the Hybrid Memory Cube Consortium is to facilitate HMC integration into a wide variety of systems, platforms and applications," said Scott Graham, general manager of Hybrid Memory Cube for Micron Technology, co-founder of the HMCC. "We are excited by Open-Silicon's efforts to enable the adoption of HMC technology."

The Open-Silicon IP offers a seamless way to interface with HMC. Supporting up to 240GBps, the high-performance HMC controller IP also offers ultra-low latency and a flexible user interface. As a fully synchronous, soft-core implementation suitable for ASICs and FPGAs, along with robust error detection and automatic retry, the core supports up to four HMC links managed by a single controller. Each link consists of 16 lanes of 10, 12.5 or 15 Gbps.

"We believe that 3D IC technology is the future of semiconductors. When we joined HMCC as one of the first developer members, we did this with the intent of enabling, and bringing to market, this revolutionary technology," said Steve Erickson, VP of IP and Platforms, Open-Silicon. "The HMC controller IP is highly configurable, and will enable our customers to enjoy greater differentiation in the market."

Author: Srinivasa Reddy N