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  Date:24th May 2012

Si2 supported design flow interoperability demo by 7 EDA companies at DAC

Seven companies to demonstrate the progress advancing design flow interoperability in the Silicon Integration Initiative (Si2) Booth #1214 at the Design Automation Conference on June 4-6, at the Moscone Center in San Francisco, CA. These companies are to showcase how Si2 standards developed by the various Si2 coalitions can provide innovative approaches to critical IC design flow issues.
Brief notes on the company's demonstrations:
1. Cadence Design Systems: To demonstrate its Silicon Realization flows, which use an OpenAccess infrastructure and leverage proven Virtuoso and Encounter technologies to maximize productivity and predictability in today's complex design projects. Witness the seamless integration of analog and digital domains with a mixed-signal design, implementation, and verification solution. Learn more about a robust and advanced low-power solution, proven to dramatically reduce overall power consumption in customer silicon and total turnaround time of chip design.

2. ICScape: To demonstrate its complete Analog and mixed-signal design platform. The analog design environment is native OA based and provides powerful schematic and layout editors. While the design environment is fully interoperable with popular simulation and verification tools, the demonstration will bring out the integration with in-house circuit simulation, top level routing, physical verification and extraction tools. The demo will highlight the integration with internal tools, and several ease of use and productivity features.

3. Invarian, Inc: To demonstrate their line of physical sign-off and analysis products built entirely with OpenAccess. With the performance and capacity of OpenAccess, the Invarian line of products (Pioneer 2D and Frontier 3D) is capable of running full chip analysis for Power, IR-drop, Temperature, and reliability. Demo will include demonstration of all these capabilities in GUI environment. Demonstration of analysis flow will provide more details on the ease of integration and compatibility for OA based tools by Invarian. Invarian will also be located in Suite 317.

4. Nangate: To showcase two major product focuses. First is the newest generation of Library Creator Platform that will support the most advanced process technology down to 22nm, with a very effective productivity increase through its support of process and layout migration. Running on Open Access infrastructure, the demonstration will explore different challenges and solutions demanded by the most complex and advanced cell layout. The other product demonstration will be the Design Optimizer (NDO), a patented analysis and netlist optimization technology that will result in significant design performance improvement. Both demonstration and product roadmap will be discussed at DAC. Scheduling is highly recommended in advance.

5. Pulsic: To demonstrate the Unity Analog Router, a GUI based, guided, constraint driven flow for automating analog layout and producing hand crafted quality layout results that analog designers would create if laid out manually. The Unity Analog Router provides analog designers with an easy to use flow that complements a skilled analog designer's experience, enabling fast device preparation and routing of hierarchical analog blocks. The intuitive set up minimizes the learning curve so analog designers can reduce layout time for large hierarchical analog blocks to a few days. The Unity Analog Router includes signal flow routing, DRC check and fix for checking and correcting DRC errors, symmetry and near symmetry routing, net tapering based on pin current density, common centroid group routing, shielding and comprehensive editing capabilities.

6. Spectral Design & Test: To demonstrate the Memory Development Platform that will lead to a >50% improvement in design productivity. All aspects of tiling, electrical analysis, characterization & view creation are consolidated into a unified environment. The MemoryCanvasTM module is a graphically driven floorplanner that encapsulates the memory designers compilation intent into a concise OpenAccess database. Schematics, LEF, GDSII, Gate level Verilog & critical path netlists are automatically generated based on the designer's inputs. The MemoryTimeTM module is a modeling, circuit analysis & characterization solution built on OpenAccess, to automatically generate RAM/ROM/CAM models, design margin statistical reports, datasheets and timing models. See how MemoryCanvas, MemoryTime complemented with MemoryIP, seamlessly interfaces with our EDA partners solutions. The demonstration will showcase a real life example of a complex memory design starting from specification, architecture development, compiler development to final deployment.

7. Synopsys: To demonstrate Galaxy IC Compiler custom co-design implementation flow for a unified cell-based and custom implementation solution featuring advanced autorouting technology. Learn how Galaxy Custom Designer tight integration with IC Compiler provides seamless full custom editing of IC Compiler designs at any stage of the flow. Custom Designer is built natively on OpenAccess to provide the industry's most open, standards-based custom design solution.

More information with agendas can be found at: http://www.si2.org/?page=1525

Author: Srinivasa Reddy N
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