Date:29th Jan 2012

Fujitsu Semiconductor uses latest DFM VLSI software from Mentor

Fujitsu Semiconductor Limited is designing its ICs using Mentor Graphics' latest Calibre physical verification and design for manufacturing (DFM) software.

Mentor higlights Calibre platform's interesting feature is it provides pattern matching for fast identification of litho hotspots and other design rule check (DRC) violations, automatic waivers for managing rule waivers during DRC, programmable electrical rule checking (PERC) for reliability verification, and the SmartFill function to realize advanced timing-aware filling for DFM.

"Exponentially increasing design complexity is something we must consider as we and our customers develop products on more advanced processes," said Hiroshi Ikeda, director of the System LSI Technology and Design Platform Development Department at Fujitsu Semiconductor Limited. "Our designers need tools that improve designer efficiency and help achieve reduced time-to-market targets. The Calibre platform addresses these needs by making complex design rule checks easier to specify, by tracking waivers automatically, and by automating electrical checks that we have been forced to perform, mostly by hand, in the past. We also believe that the Mentor SmartFill fill solution is needed to achieve faster and less intrusive DFM filling to keep up with more advanced nodes."

Fujitsu says by optimizing fill shapes for multiple objectives and across multiple layers, the Calibre SmartFill tool produces a layout that is more robust with fewer manufacturing and post-fill induced timing issues.