Date: 9th Jun 2011

Cadence has announced its products for TSMC's latest Reference Flow

Cadence Design Systems, Inc. has announced its EDA software products for TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for 28-nanometer (nm) nodes.

"The EDA360 vision calls on key industry players to work collaboratively to solve growing design complexity challenges," said Dave Desharnais, group director, product marketing, Silicon Realization at Cadence. "Our close relationship with TSMC enables us to pioneer AMS, ESL, 3D-IC and DFM solutions that are critical to the productivity and predictability of SoC design at advanced nodes. Together, we ensure customers can accelerate their 28-nm designs and successfully get them into high-volume production."

"Our new reference flows reflect significant technological advances that result from close collaboration with industry leaders like Cadence," said Suk Lee, director of Design Infrastructure Marketing at TSMC. "The combination of Cadence end-to-end solutions with our new design methodologies ensures that designers can further accelerate the development of 28-nanometer designs."

TSMC and Cadence have collaborated in the areas of electronic system level (ESL), 3D-IC implementation, design for manufacturing (DFM), and analog mixed-signal (AMS) design.

Cadence says it has developed the ESL capabilities, delivered as part of TSMC Reference Flow 12. Cadence System Development Suite features four connected platforms that enabling design engineers to co-design hardware-software semiconductor chip design.

Design engineers can go for early software development using the open SystemC language, Cadence Suite supports SoC virtual prototyping for TLM and TLM/RTL platforms. Design engineers can cut the over all power consumption using TSMC iPPA power estimation tool.

Cadence has also announced it is working in making its VLSI design tools ready for development of 20nm ICs. Cadence is hosting invitation-only customer meetings to provide an advance look at the technologies it is developing to enable production-ready 20-nanometer designs.

TSMC is now jointly working with Cadence engineers to develop IP by contributing "seed IP" so that Cadence engineer can develop them further.