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Date: 6th Jun 2011
SuVolta's MOSFET channel tech to 2x cut
power consumption of semiconductor chips
SuVolta has engineered the MOSFET current channel so that
it conducts far better than the present MOSFETs. SuVolta
says its Deeply Depleted Channel (DDC) CMOS transistor technology
as well as DDC-optimized circuits and design techniques
cuts power consumption by 2x which also results in lessening
of operating voltage by 30%. This technology can be implemented
by using the present CMOS semiconductor equipment and the
material without using expensive technologies such as EUV
lithography, FD-SOI or FinFETs. All this means the portable
devices can now stay on much longer and can operated from
low voltage sources. Semiconductor devices such as processors,
SRAMs, and SOCs, which use billions of MOSFETs can be significantly
benefited by this tech. Another strength of this tech is
present VLSI IPs can be used with this tech.
SuVolta has demonstrated SRAM blocks operating below 0.5
volts, further 0.3 volts down from presently tested 0.8V
SRAM memory chips.
SuVolta says its Deeply Depleted Channel transistor uses
a unique channel structure with significant benefits for
low power operation compared to conventional transistor
technology.
DDC sub-micron technology addresses threshold voltage control
by limiting random and other sources of dopant fluctuation
while simultaneously improving carrier mobility and reducing
device capacitance so as to maintain circuit speed at much
lower power, according to Dr. Scott Thompson, CTO of SuVolta,
SuVolta's DDC transistor tech leverages existing CMOS design
rules and process flows and also uses conventional design
tools and design flows.
SuVolta says by managing VT more effectively than possible
with a conventional transistor, adaptive body biasing can
be used to correct systematic manufacturing variations,
thus further decreasing VT variation and improving sort
yield. Dynamic body biasing can be used to reduce temperature
and aging effects, and to make power modes more effective
at enabling very low power operation, adds SuVolta.
Japanese semiconductor maker Fujitsu has licensed this
technology from SuVolta's PowerShrink low-power technology.
Fujitsu Semiconductor to make the technology available at
65nm process technology. Fujitsu Semiconductor's 65nm product
families is targeted to be available in the second half
of 2012.
To learn more on suvolta's tech visit www.suvolta.com
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