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Date: 27-05-11

Synopsys delivers 28-nm design rules and modules for TSMC Reference Flow 12.0

Synopsys, Inc. has announced that it is delivering comprehensive design enablement for TSMC's 28-nm process technology, integrated manufacturing compliance and an advanced system-level prototyping solution, with TSMC Reference Flow 12.0. New features of the flow include virtual prototyping and high-level synthesis linked to TSMC's advanced processes, expanded manufacturing compliance capabilities and full support of TSMC's latest 28-nm design rules and models within Synopsys' Galaxy Implementation Platform. With the new tool capabilities and system-level design integration, designers gain productivity, shortened time-to-market and faster time-to-volume using TSMC's 28-nm process technology.

"TSMC and Synopsys collaborated on Reference Flow 12.0 to increase productivity and design quality with an optimized design methodology for our mutual customers," said Suk Lee, director of design infrastructure marketing at TSMC. "The combination of Synopsys tools, IP and system-level design and prototyping capabilities with TSMC's complete 28-nm design infrastructure and advanced process technology provides designers with a comprehensive solution that addresses manufacturability while enabling design for optimized performance."

Synphony C Compiler high-level synthesis has been optimized for TSMC's advanced process technologies.

The flow includes a comprehensive ARM Cortex-A9 MPCore Fast Model-based reference Virtual Prototype, which has been extended with a TSMC example H.264 video subsystem. In conjunction with the included Linux SMP kernel and file system, this example serves as a practical template for early hardware/software stack integration and demonstrates the full virtual prototyping debug and analysis capabilities. Fully documented reference design examples for Synphony C Compiler are also included in the flow.

Reference Flow 12.0 includes IC Compiler's leakage optimization engine for final-stage leakage recovery on a close-to-tapeout design. Reference Flow 12.0 adds IC Validator's patented pattern-matching technology to extend the advantage of IC Compiler's In-Design physical verification by enabling fast detection and automated repair of manufacturing-limiting layout patterns.

"Designers are looking to make the most of TSMC's most advanced process nodes through a convergent and predictable path that helps them successfully develop a system-on-chip from system-level concept to silicon," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "Synopsys and TSMC team to deliver unique analysis, verification and implementation solutions in Reference Flow 12.0, offering our mutual customers an optimized path to achieve their aggressive system-on-chip design goals."

Set of Synopsys system-level, design implementation and verification tools, and IP for TSMC Reference Flow 12.0 includes:

System-Level Design:
Virtual Prototyping and DesignWare System-Level Library for SoC virtual prototyping and power/performance analysis
Synphony C Compiler high-level synthesis feeding into DesignCompiler Ultra

DesignWare IP:
DesignWare IP and Verification IP for the ARM AMBAinterconnect provides infrastructure and fabric components for AMBA 2.0 and AMBA 3 AXI3
Automated assembly of the IP using coreAssembler tool

Verification:
CustomSim and HSPICE circuit simulation with TSMC 28-nm model support
VCS with MVSIM voltage-aware simulation
MVRC low power static checking
SoC ESL verification using VCS with UVM 1.0

Physical Implementation:
IC Compiler place and route, including Zroute technology and dummy via insertion
IC Validator DRC/LVS In-Design physical verification and sign-off

RTL Synthesis and Test:
DC Ultra and Design Compiler Graphical RTL synthesis including Topographical technology and congestion optimization
DesignWare Library datapath IP
Power Compiler power optimization and multi-voltage power management
Formality equivalence checking
DFTMAX compression for test cost reduction
TetraMAX automatic test pattern generation (ATPG)

Analysis and Sign-off:
PrimeTime static timing analysis including advanced stage-based OCV
StarRC parasitic extraction with feature-scale VCMP, eDRAM tall contact, via-etch and trench contact modeling support
PrimeYield LCC for automatic lithography-hotspot and pattern-match detection and fixing, and TSMC unified LPC format support
Parasitic extraction, timing, IR-drop analysis

Rapid Yield Ramp:
Yield Explorer for physical pattern-aware, design-centric volume diagnosis isolates and prioritizes the dominant systematic failures among the scan diagnostics results
Integration of systematic defect simulation data into yield analysis to quickly capture process marginality impacts on scan failures

 

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