Date: 21st Mar 2011

Mentor Graphics tools help Fujitsu in finding IC yield loss

Mentor Graphics said the evaluation results at Fujitsu Semiconductor Ltd. shows it Tessent YieldInsight diagnosis-driven yield analysis tool can help cut the time required to determine the cause of IC yield loss.

According to Takahiro Fujimi, manager of the Product Engineering Department, Product Technology Division, Fujitsu Semiconductor: "We evaluated Mentor's yield analysis technology on a 15 million gate design manufactured on a 65 nm process. When used together with Mentor's Tessent TestKompress ATPG product, we found Tessent YieldInsight to be very effective in quickly and accurately identifying the actual physical locations of many IC failures. The product's intuitive graphical interface is consistent with traditional yield analysis techniques and enables product engineers to be more effective in identifying yield problems and determining the cause of systematic defects."

"Tessent YieldInsight is exciting new technology because it addresses time-to-market and manufacturing cost issues, both critical factors in the profitability of IC products," said Joseph Sawicki, VP and GM of Mentor's Design to Silicon division. "Customers can use the product to easily resolve problems with ramping production volume for new products, and they can use it to maximize mature product yield. Tessent YieldInsight represents an innovative new use of test data that already exists in our customers' production flows."