Date: 20th Mar 2011
JEDEC developing standards for 3D IC fabrication
JEDEC Solid State Technology Association has announced
it is working on development of standards for fabricating
3D-ICs. 3D ICs are suitable for combinations of memory with
other memory or logic. JEDEC said it has led the development
of functional, interface and packaging standards for several
generations of semiconductor memory including DRAM, FLASH
and SRAM, it has the expertise to enable 3D standards for
stacked devices and mixed technology semiconductor chips.
JEDEC is in forefront in creating standards for semiconductor
"JEDEC standards will allow high volume products to
take advantage of this exciting technology," said Subu
Iyer, IBM Fellow responsible for 3D integration at IBM.
The 3D ICs offer advantage of bandwidth, latency, power,
weight and form factor. Chipmakers are are implementing
three dimensional (3D) chip stacking utilizing Through Silicon
Via (TSV) chip to chip interconnects. "TSV technology
is on the cusp of enabling transformative performance improvements,
power reductions and dense package sizes for applications
ranging from handheld mobile devices to high-end servers,"
said Mian Quddus, Chairman of the JEDEC Board of Directors.
"Several JEDEC committees and task groups covering
a broad range of technologies have invested years of effort
in laying the groundwork for 3D-IC standards. With interest
in 3D-IC technology reaching an all-time high, now is the
time for companies to get involved and influence both the
near-term and strategic standards needed to enable and grow
the market for 3D-ICs," added Sophie Dumas, Chairman
of the JC-42.6 Subcommittee for Low Power Memories and Memory
Standardization Manager, ST-Ericsson.
The various committees formed by JEDEC includes:
The Solid State Memories Committee (JC-42) has been working
since June 2008 on definitions of standardized 3D memory
stacks for DDR3 which provide power and performance benefits
a full generation ahead of conventional technology. The
DDR4 standard will be implemented with 3D support from the
The Multiple Chip Packages Committee (JC-63) is currently
developing mixed technology pad sequence and device package
standards. An active Task Group of the Low Power Memories
Subcommittee (JC-42.6) is developing standards for Wide
I/O Mobile Memory with TSV interconnect stacked on System
on a Chip (SoC) Application Processors.
Quality & Reliability Committees:
The Silicon Devices Reliability Qualification & Monitoring
Subcommittee (JC-14.3) has been working on reliability interactions
of 3D stacks and has released JEP158: 3D Chip Stack with
Through-Silicon Vias (TSVS): Identifying, Understanding
and Evaluating Reliability Interactions. In addition, reliability
test methods developed by JC-14.1 and JC-14.2 and quality
documents developed by JC-14.4 are applicable to 3D-IC packaged
and unpackaged evaluations and qualifications.
The Mechanical Standardization Committee (JC-11) has been
working since June 2010 on Wide I/O Mobile Memory package
outline standardization, including an active Task Group
focused on Design Guide and MO creation.
For details visit www.jedec.org