Date: 13th Mar 2011

Joint collaboration in testing 3D semiconductor chips

Cascade Microtech and imec have entered into a collaborative research partnership for testing and characterization of 3D semiconductor IC test structures. Both agreed to work closely to develop test methods and methodologies for emerging 3D Through-Silicon-Via (TSV) structures, and to lead the way in development of global standards for 3D IC development and production test.

Fabricating DRAM, flash and SoC logic functions on single monolithic chip is more expensive than 3 Dimensional stacking of separate silicon dies of memory and processor, particularly if volumes are low. Just like the multi-layer PCBs, the stacked dies are connected by through-hole silicon vias (TSV). 3D stacked chip serve the growing market of tablet PCs and smartphones.
The advantages of 3D stacked chips include reduced form factor, reduced power consumption and increased bandwidth between inter-chip communications and also saves complex PCB design. Chip stacking with 3D-TSV interconnects requires a different Known-Good Die (KGD) wafer probing to support stacking in order to achieve practical stack yields demanding a different probe card architecture.

This joint research collaboration addresses the complexities of test inherent in new 3D-TSV IC designs by manufacturing and testing silicon wafers with test probe structures of 40 micron pitch and smaller. imec will use the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new 3D-TSV probe card from Cascade Microtech to characterize the TSV in the chip stacks as part of ongoing efforts to optimize 3D stacked IC performance and reliability.

"The complexity of the 3D-system supply chain is reflected in the partner portfolio of imec's 3D research program where leading IDMs, foundries, fabless companies, OSATs, equipment and material suppliers as well as EDA companies partner to develop and improve 3D technologies. A good alignment of these multi-disciplinary forces is required to make 3D system integration an industrial reality," said Erik Jan Marinissen, imec Principal Scientist. "The collaboration with Cascade Microtech in this early phase of engineering and development will enable us to identify challenges and provide solutions for test issues that are specific for 3D integrated systems. Enabling probing solutions for high-density interfaces, minimizing the impact of pre-bond testing on stacking yield and test access to buried layers are key challenges for testing 3D systems that we will address through this collaboration.

"Ongoing research is critical for Cascade Microtech's 3D-TSV solution path, and imec is a key collaboration partner for our development efforts, given its history of successful research collaboration, its superior research facilities, its commitment to the semiconductor industry and the expertise of its staff," said Michael Burger, President and CEO, Cascade Microtech, Inc. "In recent years, probing and test were viewed as a major barrier to 3D-TSV development and manufacturing. We are looking forward to breaking through the barrier, paving the way for our mutual customers to quickly achieve extremely cost-effective 3D-TSV test solutions."