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Date: 20th Dec 2010
Mentor Graphics suggests smart verification
methodologies for VLSI engineers
In VLSI domain, RTL and other pre-GDS verification job
is a no thanks job and sometimes gets monotonous but the
smart engineers can apply skills to improve verification
and make the job more interesting. Mentor Graphics is making
strong effort to improve verification process. It has tried
this by providing tools and expertise to Infineon to improve
Infineon's verification productivity and effectiveness by
assessing the status quo and by jointly establishing improved
SystemVerilog (SV) methodologies. The new tool doing some
magic is Mentor Graphics Questa functional verification
platform. The tools and the smart verification methodology
has added some smartness to the verification world.
The suggestion for the verification community from Mentor
Graphics include:
Creating a verification architecture document describing
overall strategy defining the general methods, layers, phases,
components, libraries, scripts, databases, tools, and decisions
that would be used throughout the verification effort
Build reusable verification components for all the design
under test (DUT) interfaces
Incorporate non-intrusive UPF-based power-aware logic in
the verification environment
Incorporate automatic formal technology to ease the process
of identifying the type of bugs found through formal techniques.
Incorporate verification metrics such as assertion density,
functional coverage, bug tracking, test ranking, test sorting,
and test merging to provide useful information about the
verification status, and how to monitor real verification
progress in terms of the effectiveness of each test.
Build a series of pseudo-random test case sequences through
a combination of constraints and object oriented programming
(OOP) extensions within an OVM testbench, to find bugs and
exhaustively verify the functionality of the DUT
This is what leading semiconductor vendor Infineon has
applied in its VLSI design techniques shared from Mentor
Graphics according to the release.
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